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| 型号： | MC68EC060RC50 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 105/128页 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 50MHZ 206-PGA |
| 标准包装： | 10 |
| 系列： | M680x0 |
| 处理器类型： | M680x0 32-位 |
| 速度： | 50MHz |
| 电压： | 3.3V |
| 安装类型： | 通孔 |
| 封装/外壳： | 206-BEPGA |
| 供应商设备封装： | 206-PGA（47.25x47.25） |
| 包装： | 托盘 |
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Memory Management Unit
MOTOROLA
M68060 USER’S MANUAL
4-9
For 8-Kbyte pages, the five bits of the PGI field are multiplied by 4 (shifted to the left by two
bits) and concatenated with the fetched pointer-level descriptor’s upper 25 bits to produce
the physical address of the 8-Kbyte page descriptor. The upper 19 bits of the page descrip-
tor are the page frame’s physical address. There are 32 8-Kbyte page descriptors in a page-
level table.
Similarly, for 4-Kbyte pages, the six bits of the PGI field are multiplied by 4 (shifted to the left
by two bits) and concatenated with the fetched pointer-level descriptor’s upper 24 bits to pro-
duce the physical address of the 4-Kbyte page descriptor. The upper 20 bits of the page
descriptor are the page frame’s physical address. There are 64 4-Kbyte page descriptors in
a page-level table.
Write-protect status is accumulated from each level’s descriptor and combined with the sta-
tus from the page descriptor to form the ATC entry status. The MC68060 creates the ATC
entry from the page frame address and the associated status bits and uses this address and
attributes to generate a bus access. Refer to 4.3 Address Translation Caches for details
on ATC entries.
If the descriptor from a page table is an indirect descriptor, the page descriptor pointed to by
this descriptor is fetched. Invalid descriptors can be used at any level of the tree except the
root. When a table search for a normal translation encounters an invalid descriptor, the pro-
cessor takes an access error exception. The invalid descriptor can be used to identify either
a page or branch of the tree that has been stored on an external device and is not resident
in memory or a portion of the translation table that has not yet been defined. In these two
cases, the exception routine can either restore the page from disk or add to the translation
table. Figure 4-8 and Figure 4-9 illustrate detailed flowcharts of table search and descriptor
fetch operations.
A table search terminates successfully when a page descriptor is encountered. The occur-
rence of an invalid descriptor or a transfer error acknowledge also terminates a table search,
and the MC68060 takes an access error exception immediately on the data access and is
delayed for instruction fetches until the instruction is ready to be executed. The exception
handler should distinguish between anticipated conditions and true error conditions. The
exception handler can correct an invalid descriptor that indicates a nonresident page or one
that identifies a portion of the translation table yet to be allocated. An access error due to a
system malfunction can require the exception handler to write an error message and termi-
nate the task. The fault status long word (FSLW) of the access error stack frame provides
detailed information regarding the cause of the exception. Refer to Section 8 Exception
Processing for more information on exception handling.
The processor does not use the data cache when performing a table search. Therefore,
translation tables must not be placed in copyback space, since the normal accesses which
build the translation tables would be cached and not written to external memory, but the pro-
cessor only uses tables in external memory. This is a functional difference between the
MC68060 and the MC68040.
Table and page descriptors must not be left in a state that is incoherent to the processor.
Violation of this restriction can result in an undefined operation. Page descriptors must not
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