- 您现在的位置：买卖IC网 > PDF目录4100 > MC68EC060RC50 (Freescale Semiconductor)IC MPU 32BIT 50MHZ 206-PGA PDF资料下载
参数资料
| 型号： | MC68EC060RC50 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 82/128页 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 50MHZ 206-PGA |
| 标准包装： | 10 |
| 系列： | M680x0 |
| 处理器类型： | M680x0 32-位 |
| 速度： | 50MHz |
| 电压： | 3.3V |
| 安装类型： | 通孔 |
| 封装/外壳： | 206-BEPGA |
| 供应商设备封装： | 206-PGA（47.25x47.25） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页当前第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页
Signal Description
MOTOROLA
M68060 USER’S MANUAL
2-11
2.7 ARBITRATION SIGNALS
The following control signals support bus mastership control by an external arbiter over the
MC68060. Refer to Section 7 Bus Operation for detailed information about the relationship
of the arbitration signals to bus operation.
2.7.1 Bus Request (BR)
This output signal indicates to an external arbiter that the processor needs to become bus
master for one or more bus cycles. BR is negated when the MC68060 begins an access to
the external bus with no other internal accesses pending, and BR remains negated until
another internal request occurs. The assertion and negation of BR are independent of bus
activity and there are some situations in which the MC68060 asserts BR and then negates
it without having run a bus cycle; this is a disregard request condition. Refer to Section 7
Bus Operation for details about this state.
2.7.2 Bus Grant (BG)
This input signal from an external arbiter indicates that the bus is available to the MC68060
as soon as the current bus cycle completes. The MC68060 assumes bus ownership when
BG is asserted and BB is negated, when BG is asserted and a TS-BTT pair (TS asserted,
followed by BTT asserted) has occurred in the past without another assertion of TS, or when
BG and BTT are asserted and TS is negated. The MC68060 indicates its ownership of the
bus by asserting BB. When the external arbiter negates BG, the MC68060 relinquishes the
bus as soon as the current bus cycle is complete unless a locked sequence of bus cycles is
in progress with BGR negated. In this case, the MC68060 will complete the entire sequence
of locked bus cycles and then indicate that it is relinquishing the bus by asserting BTT and
negating BB.
2.7.3 Bus Grant Relinquish Control (BGR)
This input signal is a qualifier for BG and indicates to the MC68060 the degree of necessity
for relinquishing bus ownership when BG is negated by an external arbiter. BGR controls
MC68060 behavior when BG is negated during sequences of locked bus cycles (LOCK
asserted). When the external arbiter negates BG during a series of locked bus cycles, the
assertion of BGR will cause the MC68060 to relinquish the bus on the last transfer of the
current bus cycle, even though the MC68060 had intended the series to be locked. If BGR
remains negated when BG is negated during locked transfers, then the MC68060 will not
relinquish the bus until the series of locked bus cycles is complete.
2.7.4 Bus Tenure Termination (BTT)
This three-state bidirectional signal is asserted for one clock-enabled clock period and
negated for one clock-enabled clock period to indicate that the MC68060 has relinquished
its bus tenure following the negation of BG by an external arbiter. At all other times, BTT is
in a high-impedance state. When an alternate master is controlling the bus, the MC68060
samples BTT as an input to maintain internal state information and to monitor when the
MC68060 may become the bus master. To properly maintain this internal state information,
all masters on the bus must have their TS signals tied together and their BTT signals tied
together so the MC68060 can keep track of TS-BTT pairs.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT71V65803S133BGG8 | IC SRAM 9MBIT 133MHZ 119BGA |
| MPC8270ZUUPEA | IC MPU POWERQUICC II 480-TBGA |
| IDT71V65803S133BG8 | IC SRAM 9MBIT 133MHZ 119BGA |
| MPC860PCZQ66D4 | IC MPU PWRQUICC 66MHZ 357-PBGA |
| IDT71V65803S100BGG8 | IC SRAM 9MBIT 100MHZ 119BGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68EC060RC66 | 功能描述:微处理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC68EC060RC75 | 功能描述:微处理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC68EC060ZU50 | 功能描述:IC MPU 68K 50MHZ 304-TBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:M680x0 标准包装:1 系列:MPC85xx 处理器类型:32-位 MPC85xx PowerQUICC III 特点:- 速度:1.2GHz 电压:1.1V 安装类型:表面贴装 封装/外壳:783-BBGA，FCBGA 供应商设备封装:783-FCPBGA（29x29） 包装:托盘 |
| MC68EC060ZU66 | 功能描述:微处理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MC68EC060ZU75 | 功能描述:微处理器 - MPU 32B W/ CACHE RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
发布紧急采购，3分钟左右您将得到回复。