参数资料
型号: MCM16Y1BACFT16
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP160
封装: QFP-160
文件页数: 101/138页
文件大小: 784K
代理商: MCM16Y1BACFT16
MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
65
Because ADDR20 = ADDR19 in the CPU16, maximum block size is 512 Kbytes. Because ADDR[23:20]
follow the logic state of ADDR19, if all 24 address lines are used, addresses from $080000 to $F7FFFF
are inaccessible.
3.10.4 Option Registers
The option registers contain eight elds that determine timing of and conditions for assertion of chip se-
lect signals. These make the chip selects useful for generating peripheral control signals. Certain con-
straints set by elds in the base address register and in the option register must be satised in order to
assert a chip select signal, and to provide DSACK or autovector support.
The option register for CSBOOT, CSORBT, contains special reset values that support bootstrap opera-
tions from peripheral memory devices.
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode selected
1 = Synchronous mode selected
In asynchronous mode, the chip select is asserted synchronized with AS or DS.
In synchronous mode, the DSACK field is not used, because a bus cycle is only performed as a syn-
chronous operation. When a match condition occurs on a chip select programmed for synchronous op-
eration, the chip select signals the EBI that an E-clock cycle is pending.
BYTE — Upper/Lower Byte Option
This field is used only when the chip select 16-bit port option is selected in the pin assignment register.
The following table lists upper/lower byte options.
R/W — Read/Write
This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.
The table below shows the options.
CSORBT — Chip Select Option Register Boot ROM
$YFFA4A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
AVEC
RESET:
0
1
0
1
0
1
0
CSOR0 – CSOR10 — Chip Select Option Registers
$YFFA4E–$YFFA76
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
AVEC
RESET:
0
Byte
Description
00
Disable
01
Lower Byte
10
Upper Byte
11
Both Bytes
R/W
Description
00
Reserved
01
Read Only
10
Write Only
11
Read/Write
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