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| 型号： | MCM16Y1BACFT16 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 17/138页 |
| 文件大小： | 784K |
| 代理商： | MCM16Y1BACFT16 |
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MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
113
8 Standby RAM with TPU Emulation
The standby RAM with TPU emulation module (TPURAM) contains a 2-Kbyte array of fast (two bus cy-
cle) static RAM, which is especially useful for system stacks and variable storage. The RAM can be
used to emulate TPU microcode ROM. The TPURAM can be mapped to any 2-Kbyte boundary in the
address map, but must not overlap the module control registers — overlap makes the registers inac-
cessible. TPURAM responds to both program and data space accesses. Data can be read or written in
bytes, word, or long words. The RAM is powered by VDD in normal operation. During power-down, the
RAM contents are maintained by power on standby voltage pin VSTBY. Power switching between sourc-
es is automatic.
8.1 TPURAM Register Block
TPURAM control registers occupy a 64-byte block. There are three TPURAM control registers in the
block: the RAM module configuration register (TRAMMCR), the RAM test register (TRAMTST), and the
RAM array base address register (TRAMBAR). The rest of the register block contains unimplemented
register locations. Unimplemented register addresses are read as zeros, and writes to them have no
effect.
Y = M111, where M is the state of the modmap bit in the module configuration register of the
single-chip integration module. In an MC68HC16Y1 system, M must always be set to one.
8.2 TPURAM Registers
Access to the TPURAM array is controlled by the RASP field in the TRAMMCR.
Bits in TRAMMCR determine whether the RAM is in low-power stop mode or normal mode, indicate fail-
ure of standby RAM power, and determine in which address space the array resides. Reads of unim-
plemented bits always return zeros. Writes do not affect unimplemented bits.
STOP — Stop Control Bit
0 = RAM array operates normally.
1 = RAM array enters low-power stop mode.
This bit controls whether the RAM array is in low-power consumption mode or operating normally. Reset
state is zero, for normal operation. In stop mode, the array retains its contents, but cannot be read or
written by the CPU.
Table 31 TPURAM Control Register Address Map
Address
15
8 7
0
$YFFB00
RAM MODULE CONFIGURATION REGISTER (TRAMMCR)
$YFFB02
RAM TEST REGISTER (TRAMTST)
$YFFB04
RAM BASE ADDRESS AND STATUS REGISTER (TRAMBAR)
$YFFB06–
$YFFB3F
NOT IMPLEMENTED
TRAMMCR — RAM Module Configuration Register
$YFFB00
15
12
8
7
0
STOP
PDS
RASP
NOT USED
RESET:
0
U
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相关代理商/技术参数 |
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| MCM16Z2BCFC16 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Symbols and Operators, CPU16 Register Mnemonics |
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| MCM16Z2BCFC20B1 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series users manual |
| MCM16Z2BCFC25 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series users manual |
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