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| 型号： | MCM16Y1BACFT16 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 69/138页 |
| 文件大小： | 784K |
| 代理商： | MCM16Y1BACFT16 |
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MOTOROLA
MC68HC16Y1
36
MC68HC16Y1TS/D
RWD — Read/Write Disable
0 = R/W signal operates normally
1 = R/W signal placed in high-impedance state.
RWD is cleared to zero when the MCU is in an expanded mode, and set to one in single-chip mode.
RWD can be written only once after reset.
IARB[3:0] — Interrupt Arbitration
Each module that can generate interrupts, including the SCIM, has an IARB field. Each IARB field can
be assigned a value from $0 to $F. During an interrupt acknowledge cycle, IARB permits arbitration
among simultaneous interrupts of the same priority level. The reset value of the SCIM IARB field is $F.
This prevents SCIM interrupts from being discarded. Initialization software must set the IARB field to a
lower value if lower priority interrupts are to be arbitrated.
The reset status register contains a bit for each reset source in the MCU. A bit set to one indicates what
type of reset has occurred. When multiple reset sources occur at the same time, more than one bit in
RSR can be set. The reset status register is updated by the reset control logic when the MCU comes
out of reset. This register can be read at any time. A write has no effect.
EXT — External Reset
Reset was caused by an external signal.
POW — Power-Up Reset
Reset was caused by the power-up reset circuit.
SW — Software Watchdog Reset
Reset was caused by the software watchdog circuit.
HLT — Halt Monitor Reset
Reset was caused by the system protection submodule halt monitor.
LOC — Loss of Clock Reset
Reset was caused by loss of clock submodule frequency reference. This reset can only occur if the
RSTEN bit in the clock submodule is set and the VCO is enabled.
SYS — System Reset
Reset was caused by the CPU RESET instruction. System reset does not load a reset vector or affect
any internal CPU registers or SIM configuration registers, but does reset external devices and other in-
ternal modules.
3.2 Operating Modes
During reset, the SCIM configures itself according to the states of the DATA, BERR, MODCLK, and
BKPT pins. DATA[11:0] provide pin configuration information. BERR, MODCLK, and BKPT determine
basic operation.
The SCIM can be configured to operate in one of three modes: 16-bit expanded, 8-bit expanded, and
single chip. Operating mode is determined by the value of the DATA1 and BERR signals coming out of
reset.
RSR — Reset Status Register
$YFFA07
76543210
EXT
POW
SW
HLT
0
LOC
SYS
TST
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相关代理商/技术参数 |
参数描述 |
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| MCM16Z2BCFC16 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Symbols and Operators, CPU16 Register Mnemonics |
| MCM16Z2BCFC16B1 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Symbols and Operators, CPU16 Register Mnemonics |
| MCM16Z2BCFC20 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Symbols and Operators, CPU16 Register Mnemonics |
| MCM16Z2BCFC20B1 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series users manual |
| MCM16Z2BCFC25 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series users manual |
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