参数资料
型号: MCM16Y1BACFT16
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP160
封装: QFP-160
文件页数: 78/138页
文件大小: 784K
代理商: MCM16Y1BACFT16
MOTOROLA
MC68HC16Y1
44
MC68HC16Y1TS/D
3.4.1 Clock Sources
The state of the clock mode (MODCLK) pin during reset determines clock source. When MODCLK is
held high during reset, the clock synthesizer generates a clock signal from either a crystal oscillator or
an external reference input — clock synthesizer control register SYNCR determines operating frequen-
cy and various modes of operation. When MODCLK is held low during reset, the clock synthesizer is
disabled, and an external system clock signal must be applied — SYNCR control bits have no effect.
A reference crystal must be connected between the EXTAL and XTAL pins in order to use the internal
oscillator. Use of a 32.768 kHz watch crystal is recommended — these crystals are readily available
and inexpensive.
If an external reference signal or an external system clock signal is applied via the EXTAL pin, the XTAL
pin must be left floating. External reference signal frequency must be less than or equal to maximum
specified reference frequency. External system clock signal frequency must be less than or equal to
maximum specified system clock frequency.
When an external system clock signal is applied (PLL not used), duty cycle of the input is critical, espe-
cially at operating frequencies close to maximum. The relationship between clock signal duty cycle and
clock signal period is expressed:
Minimum external clock period =
minimum external clock high/low time
50% – percentage variation of external clock input duty cycle
3.4.2 Clock Synthesizer Operation
A voltage controlled oscillator (VCO) generates the system clock signal. A portion of the clock signal is
fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator.
The other phase comparator input is a reference signal, either from the internal oscillator or from an
external source. The comparator generates a control signal proportional to the difference in phase be-
tween its two inputs. The signal is low-pass filtered and used to correct VCO output frequency.
The synthesizer locks when VCO frequency is identical to reference frequency. Lock time is affected by
the filter time constant and by the amount of difference between the two comparator inputs. Whenever
comparator input changes, the synthesizer must re-lock. Lock status is shown by the SLOCK bit in SYN-
CR.
The MC68HC16Y1 does not come out of reset state until the synthesizer locks. Crystal type, character-
istic frequency, and layout of external oscillator circuitry affect lock time.
The low-pass filter requires an external low-leakage capacitor, typically 0.1
F, connected between the
XFC and VDDSYN pins.
VDDSYN is used to power the clock circuits. A separate power source increases MCU noise immunity
and can be used to run the clock when the MCU is powered down. A quiet power supply must be used
as the VDDSYN source, since PLL stability depends on the VCO, which uses this supply. Adequate ex-
ternal bypass capacitors should be placed as close as possible to the VDDSYN pin to assure stable op-
erating frequency.
When the clock synthesizer is used, control register SYNCR determines operating frequency and vari-
ous modes of operation. Because the CPU16 in the MC68HC16Y1 operates only in supervisor mode,
SYNCR can be read or written at any time.
The SYNCR X bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting
X doubles clock speed without changing VCO speed — there is no VCO relock delay. The SYNCR W
bit controls a 3-bit prescaler in the feedback divider. Setting W increases VCO speed by a factor of four.
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