参数资料
型号: MCM16Y1BACFT16
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP160
封装: QFP-160
文件页数: 80/138页
文件大小: 784K
代理商: MCM16Y1BACFT16
MOTOROLA
MC68HC16Y1
46
MC68HC16Y1TS/D
SLOCK — Synthesizer Lock Flag
0 = VCO is enabled, but has not locked.
1 = VCO has locked on the desired frequency (or system clock is external).
The MCU maintains reset state until the synthesizer locks, but SLOCK does not indicate synthesizer
lock status until after the user writes to SYNCR.
RSTEN — Reset Enable
0 = Loss of crystal causes the MCU to operate in limp mode.
1 = Loss of crystal causes system reset.
STSCIM — Stop Mode System Integration Clock
0 = When LPSTOP is executed, the SCIM clock is driven from the crystal oscillator and the VCO is
turned off to conserve power.
1 = When LPSTOP is executed, the SCIM clock is driven from the VCO.
STEXT — Stop Mode External Clock
0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve power.
1 = When LPSTOP is executed, the CLKOUT signal is driven from the SCIM clock, as determined
by the state of the STSCIM bit.
3.4.4 Periodic Interrupt Timer
The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing
for the PIT is provided by a programmable prescaler driven by the system clock.
This register contains information concerning periodic interrupt priority and vectoring. Bits [10:0] can be
read or written at any time. Bits [15:11] are unimplemented and always return zero.
PIRQL[2:0] — Periodic Interrupt Request Level
The table below shows what interrupt request level is asserted when a periodic interrupt is generated.
If a PIT interrupt and an external IRQ of the same priority occur simultaneously, the PIT interrupt is ser-
viced first. The periodic timer continues to run when the interrupt is disabled.
PIV[7:0] — Periodic Interrupt Vector
The bits of this field contain the vector generated in response to an interrupt from the periodic timer.
When the SCIM responds, the periodic interrupt vector is placed on the bus.
PICR — Periodic Interrupt Control Register
$YFFA22
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIRQL
PIV
RESET:
0
1
PIRQL
Interrupt Request Level
000
Periodic Interrupt Disabled
001
Interrupt Request Level 1
010
Interrupt Request Level 2
011
Interrupt Request Level 3
100
Interrupt Request Level 4
101
Interrupt Request Level 5
110
Interrupt Request Level 6
111
Interrupt Request Level 7
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