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参数资料
| 型号： | MCM16Y1BACFT16 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 15/138页 |
| 文件大小： | 784K |
| 代理商： | MCM16Y1BACFT16 |
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MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
111
RAF — Receiver Active Flag
0 = SCI receiver is idle.
1 = SCI receiver is busy.
RAF indicates whether the SCI receiver is busy. It is set when the receiver detects a possible start bit
and is cleared when the chosen type of idle line is detected. RAF can be used to reduce collisions in
systems with multiple masters.
IDLE — Idle-Line Detected Flag
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
IDLE is disabled when RWU in SCCR1 is set. IDLE is set when the SCI receiver detects the idle-line
condition specified by ILT in SCCR1. If cleared, IDLE will not set again until after RDRF is set. RDRF
is set when a break is received, so that a subsequent idle line can be detected.
OR — Overrun Error Flag
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
OR is set when a new byte is ready to be transferred from the receive serial shifter to the RDR, and
RDRF is still set. Data transfer is inhibited until OR is cleared. Previous data in RDR remains valid, but
data received during overrun condition (including the byte that set OR) is lost.
NF — Noise Error Flag
0 = No noise detected on the received data.
1 = Noise occurred on the received data.
NF is set when the SCI receiver detects noise on a valid start bit, on any data bit, or on a stop bit. It is
not set by noise on the idle line or on invalid start bits. Each bit is sampled three times. If all three sam-
ples are not the same logic level, the majority value is used for the received data value, and NF is set.
NF is not set until an entire frame is received and RDRF is set.
FE — Framing Error Flag
1 = Framing error or break occurred on the received data.
0 = No framing error on the received data.
FE is set when the SCI receiver detects a zero where a stop bit was to have occurred. FE is not set until
the entire frame is received and RDRF is set. A break can also cause FE to be set. It is possible to miss
a framing error if RXD happens to be at logic level one at the time when the stop bit is expected.
PF — Parity Error Flag
1 = Parity error occurred on the received data.
0 = No parity error on the received data.
PF is set when the SCI receiver detects a parity error. PF is not set until the entire frame is received and
RDRF is set.
Each SCDR consists of two data registers at the same address. RDR is a read-only register that con-
tains data received by the SCI serial interface. The data comes into the receive serial shifter and is
transferred to RDR. TDR is a write-only register that contains data to be transmitted. The data is first
written to TDR, then transferred to the transmit serial shifter, where additional format bits are added be-
fore transmission. R[7:0]/T[7:0] contain either the first eight data bits received when SCDR is read, or
the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is config-
ured for 9-bit operation. When it is configured for 8-bit operation, they have no meaning or effect.
SCDRA, SCDRB — SCI Data Register
$YFFC1E, $YFFC2E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R8/T8
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
RESET:
0
U
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| MCM16Z2BCFC20B1 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series users manual |
| MCM16Z2BCFC25 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series users manual |
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