参数资料
型号: MCM16Y1BACFT16
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP160
封装: QFP-160
文件页数: 90/138页
文件大小: 784K
代理商: MCM16Y1BACFT16
MC68HC16Y1
MOTOROLA
MC68HC16Y1TS/D
55
knowledge cycle is transferred to the external bus, an external device must decode the mask value and
respond with a vector number, then generate bus cycle termination signals. If the device does not re-
spond in time, a spurious interrupt exception is taken.
The periodic interrupt timer (PIT) in the SCIM can generate internal interrupt requests of specific priority
at predetermined intervals. By hardware convention, PIT interrupts are serviced before external inter-
rupt service requests of the same priority. Refer to 3.4.4 Periodic Interrupt Timer for more information.
3.7.2 Interrupt Processing Summary
A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt
service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. Processor state is stacked, then the CCR PK extension field is cleared.
C. The interrupt acknowledge cycle begins:
1.
FC[2:0] are driven to %111 (CPU space) encoding.
2.
The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16] = %1111,
which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]
= %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged;
and ADDR0 = %1.
3.
Request priority is latched into the CCR IP field from the address bus.
D. Modules or external peripherals that have requested interrupt service decode the priority value
in ADDR[3:1]. If request priority is the same as the priority value in the address, IARB contention
takes place. When there is no contention, the spurious interrupt monitor asserts BERR, and a
spurious interrupt exception is processed.
E. After arbitration, the interrupt acknowledge cycle can be completed in one of three ways:
1.
The dominant interrupt source supplies a vector number and DSACKx signals appropriate
to the access. The CPU16 acquires the vector number.
2.
The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source
or the pin can be tied low), and the CPU16 generates an autovector number corresponding
to interrupt priority.
3.
The bus monitor asserts BERR and the CPU16 generates the spurious interrupt vector
number.
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor transfers control to
the exception handler routine.
3.8 General-Purpose Input/Output
The SCIM contains six general-purpose input/output ports: ports A, B, E, F, G, and H. (Port C, an output-
only port, is included under the discussion of chip selects.) Ports A, B, and G are available in single-chip
mode only, and Port H is available in single-chip or 8-bit expanded modes only. Ports E, F, G, and H
have an associated data direction register (DDR) to configure each pin as input or output. Ports A and
B share a DDR that configures each port as input or output. Ports E and F have associated pin assign-
ment registers which configure each pin as digital I/O or an alternate function. Port F has an edge-detect
flag register which indicates whether a transition has occurred on any of its pins.
The following table shows the shared functions of the general-purpose I/O ports and the modes in which
they are available.
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