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| 型号： | MT28C3224P20 |
| 厂商： | Micron Technology, Inc. |
| 元件分类： | DRAM |
| 英文描述： | FLASH AND SRAM COMBO MEMORY |
| 中文描述： | 闪存和SRAM式内存 |
| 文件页数： | 10/42页 |
| 文件大小： | 498K |
| 代理商： | MT28C3224P20 |
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10
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
FLASH MEMORY OPERATING MODES
COMMAND STATE MACHINE
Commands are issued to the command state ma-
chine (CSM) using standard microprocessor write tim-
ings. The CSM acts as an interface between external
microprocessors and the internal write state machine
(WSM). The available commands are listed in Table 3,
their definitions are given in Table 4 and their descrip-
tions in Table 5. Program and erase algorithms are
automated by the on-chip WSM. For more specific in-
formation about the CSM transition states, see Micron
technical note TN-28-33, “Command State Machine
Description and Command Definition.”
Once a valid PROGRAM/ERASE command is en-
tered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to con-
trol the device internally. A command is valid only if the
exact sequence of WRITEs is completed. After the WSM
completes its task, the write state machine status
(WSMS) bit (SR7) (see Table 7) is set to a logic HIGH
level (V
IH
), allowing the CSM to respond to the full com-
mand set again.
OPERATIONS
Device operations are selected by entering a stan-
dard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/Os DQ0–DQ7. The number of bus cycles required to
activate a command is typically one or two. The first
operation is always a WRITE. Control signals F_CE#
and F_WE# must be at a logic LOW level (V
IL
), and F_OE#
and F_RP# must be at logic HIGH (V
IH
). The second
operation, when needed, can be a WRITE or a READ
depending upon the command. During a READ opera-
tion, control signals F_CE# and F_OE# must be at a
logic LOW level (V
IL
), and F_WE# and F_RP# must be at
logic HIGH (V
IH
).
Table 6 illustrates the bus operations for all the
modes: write, read, reset, standby, and output disable.
When the device is powered up, internal reset cir-
cuitry initializes the chip to a read array mode of opera-
tion. Changing the mode of operation requires that a
command code be entered into the CSM. For each one
of the two Flash memory partitions, an on-chip status
register is available. These two registers allow the moni-
toring of the progress of various operations that can
take place on a memory bank. One of the two status
registers is interrogated by entering a READ STATUS
REGISTER command onto the CSM (cycle 1), specify-
ing an address within the memory partition boundary,
and
reading the register data on I/O pins DQ0–DQ7
(cycle 2). Status register bits SR0-SR7 correspond to
DQ0–DQ7 (see Table 7).
COMMAND DEFINITION
Once a specific command code has been entered,
the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 4 for the CSM command defini-
tions and data for each of the bus cycles.
STATUS REGISTER
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling F_OE# and F_CE# and reading the result-
ing status code on I/Os DQ0–DQ7. The high-order I/Os
(DQ8–DQ15) are set to 00h internally, so only the low-
Table 3
Command State Machine Codes For Device Mode Selection
COMMAND DQ0–DQ7
40h/10h
20h
50h
60h
70h
90h
98h
B0h
C0h
D0h
FFh
CODE ON DEVICE MODE
Program setup/alternate program setup
Block erase setup
Clear status register
Protection configuration setup
Read status register
Read protection configuration register
Read query
Program/erase suspend
Protection register program/lock
Program/erase resume – erase confirm
Read array
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相关代理商/技术参数 |
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|---|---|
| MT28C3224P20FL-80 BET | 制造商:Micron Technology Inc 功能描述: |
| MT28C3224P20FL-80 BET TR | 制造商:Micron Technology Inc 功能描述: |
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| MT28C6428P18FM-85 BET | 制造商:Micron Technology Inc 功能描述: |
| MT28C6428P18FM-85 BET TR | 制造商:Micron Technology Inc 功能描述: |
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