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| 型号： | MT28C3224P20 |
| 厂商： | Micron Technology, Inc. |
| 元件分类： | DRAM |
| 英文描述： | FLASH AND SRAM COMBO MEMORY |
| 中文描述： | 闪存和SRAM式内存 |
| 文件页数： | 24/42页 |
| 文件大小： | 498K |
| 代理商： | MT28C3224P20 |
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F
24
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
STANDBY MODE
Icc supply current is reduced by applying a logic
HIGH level on F_CE# and F_RP# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on F_CE#
and F_RP# reduces the current to I
CC
3
(MAX). If the
device is deselected during an ERASE operation or dur-
ing programming, the device continues to draw cur-
rent until the operation is complete.
AUTOMATIC POWER SAVE (APS) MODE
Substantial power savings are realized during peri-
ods when the Flash array is not being read and the
device is in the active mode. During this time the de-
vice switches to the automatic power save (APS) mode.
When the device switches to this mode, I
CC
is reduced
to a level comparable to I
CC
3
. Further power savings can
be realized by applying a logic HIGH level on CE# to
place the device in standby mode. The low level of
power is maintained until another operation is initi-
ated. In this mode, the I/Os retain the data from the
last memory address read until a new address is read.
This mode is entered automatically if no addresses or
control signals toggle.
V
PP
/V
CC
PROGRAM AND ERASE
VOLTAGES
The Flash memory devices provide in-system
programming and erase with V
PP
in the 0.9V–2.2V range.
In addition to the flexible block locking, the V
PP
pro-
gramming voltage can be held LOW for absolute hard-
ware write protection of all blocks in the Flash device.
When V
PP
is below V
PPLK
, any PROGRAM or ERASE op-
eration results in an error, prompting the correspond-
ing status register bit (SR3) to be set.
A factory option provides in-system programming
and erase with V
PP
in the 0.0V–2.2V range.
V
PP
at 12V ±5% (V
PP
2
) is supported for a maximum
of 100 cycles and 10 cumulative hours. The device
can withstand 100,000 WRITE/ERASE operations when
V
PP
= V
CC
.
During WRITE and ERASE operations, the WSM
monitors the V
PP
voltage level. WRITE/ERASE opera-
tions are allowed only when V
PP
is within the ranges
specified in Table 10.
When V
CC
is below V
LKO
or V
PP
is below V
PPLK
, any
WRITE/ERASE operation is prevented.
DEVICE RESET
To correctly reset the device, the RST# signal must
be asserted (RST# = V
IL
) for a minimum of
t
RP.
After
reset, the device can be accessed for a READ operation
with a delayed access time of
t
RWH from the rising edge
of RST#. The circuitry used for generating the RST#
signal needs to be common with the rest of the system
reset to ensure that correct system initialization occurs.
Please refer to the timing diagram for further details.
POWER-UP SEQUENCE
The following power-up sequence is recommended
to properly initialize internal chip operations:
At power-up, RST# should be kept at V
IL
for 2μs
after V
CC
reaches V
CC
(MIN).
V
CC
Q should not come up before V
CC
.
V
PP
should be kept at V
IL
to maximize data
integrity.
When the power-up sequence is completed, RST#
should be brought to V
IH
. To ensure proper power-up,
the rise time of RST# (10%–90%) should be < 10μs.
Table 10
V
PP
Ranges (V)
DEVICE
In-System
In-Factory
MIN
0.9
11.4
MAX
2.2
12.6
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