- 您现在的位置：买卖IC网 > PDF目录385639 > MT28C3224P20 (Micron Technology, Inc.) FLASH AND SRAM COMBO MEMORY PDF资料下载
参数资料
| 型号： | MT28C3224P20 |
| 厂商： | Micron Technology, Inc. |
| 元件分类： | DRAM |
| 英文描述： | FLASH AND SRAM COMBO MEMORY |
| 中文描述： | 闪存和SRAM式内存 |
| 文件页数： | 14/42页 |
| 文件大小： | 498K |
| 代理商： | MT28C3224P20 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页
F
14
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
CLEAR STATUS REGISTER
The internal circuitry can set, but not clear, the block
lock status bit (SR1), the V
PP
status bit (SR3), the pro-
gram status bit (SR4), and the erase status bit (SR5) of
the status register. The CLEAR STATUS REGISTER com-
mand (50h) allows the external microprocessor to clear
these status bits and synchronize to the internal op-
erations. When the status bits are cleared, the device
returns to the read array mode.
READ OPERATIONS
The following
READ operations are available: READ
ARRAY, READ PROTECTION CONFIGURATION REG-
ISTER, READ QUERY and READ STATUS REGISTER.
READ ARRAY
The array is read by entering the command code
FFh on DQ0–DQ7. Control signals F_CE# and F_OE#
must be at a logic LOW level (V
IL
), and F_WE# and F_RP#
must be at a logic HIGH level (V
IH
) to read data from the
array. Data is available on DQ0–DQ15. Any valid ad-
dress within any of the blocks selects that address and
allows data to be read from that address. Upon initial
power-up or device reset, the device defaults to the
read array mode.
READ CHIP PROTECTION IDENTIFICATION DATA
The chip identification mode outputs three types
of information: the manufacturer/device identifier, the
block locking status, and the protection register. Two
bus cycles are required for this operation: the chip iden-
tification data is read by entering the command code
90h on DQ0–DQ7 to the bank containing address 00h
and the identification code address on the address
lines. Control signals F_CE# and F_OE# must be at a
logic LOW level (V
IL
), and F_WE# and F_RP# must be at
a logic HIGH level (V
IH
) to read data from the protection
configuration register. Data is available on DQ0–DQ15.
After data is read from the protection configuration
register, the READ ARRAY command, FFh, must be is-
sued to the bank containing address 00h prior to issu-
ing other commands. See Table 9 for further details.
READ QUERY
The read query mode outputs common flash inter-
face (CFI) data when the device is read (see Table 11).
Two bus cycles are required for this operation. It is
possible to access the query by writing the read query
command code 98h on DQ0–DQ7 to the bank contain-
ing address 0h. Control signals F_CE# and F_OE# must
be at a logic LOW level (V
IL
), and F_WE# and F_RP#
must be at a logic HIGH level (V
IH
) to read data from the
query. The CFI data structure contains information
such as block size, density, command set, and electri-
cal specifications. To return to read array mode, write
the read array command code FFh on DQ0–DQ7.
READ STATUS REGISTER
The status register is read by entering the command
code 70h on DQ0–DQ7. Two bus cycles are required for
this operation: one to enter the command code and a
second to read the status register. In a READ cycle, the
address is latched and register data is updated on the
falling edge of F_OE# or F_CE#, whichever occurs last.
相关PDF资料 |
PDF描述 |
|---|---|
| MT28F200B3 | FLASH MEMORY |
| MT28F200B5 | FLASH MEMORY |
| MT28F320A18 | FLASH MEMORY |
| MT2D18 | 1 Meg x 8 DRAM Module(5V，1M x 8 动态RAM模块) |
| MT46V16M4 | 4 Meg x 4 x 4 banks DDR SDRAM(4 M x 4 x 4组，双数据速率同步动态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT28C3224P20FL-80 BET | 制造商:Micron Technology Inc 功能描述: |
| MT28C3224P20FL-80 BET TR | 制造商:Micron Technology Inc 功能描述: |
| MT28C6428P18 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:FLASH AND SRAM COMBO MEMORY |
| MT28C6428P18FM-85 BET | 制造商:Micron Technology Inc 功能描述: |
| MT28C6428P18FM-85 BET TR | 制造商:Micron Technology Inc 功能描述: |
发布紧急采购，3分钟左右您将得到回复。