F
17
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
Figure 4
Automated Word Programming
Flowchart
NOTE:
1. Full status register check can be done after each word or after a sequence of words.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation
attempts.
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE
PROGRAM
SETUP
WRITE
WRITE
DATA
Data =
Addr =
40h or 10h
Address of word to be
programmed
Word to be
programmed
Address of word to be
programmed
Status register data;
toggle OE# or CE# to update
status register.
Check SR7
1 = Ready, 0 = Busy
Data =
Addr =
READ
Standby
Repeat for subsequent words.
Write FFh after the last word programming operation
to reset the device to read array mode.
BUS
OPERATION COMMAND COMMENTS
Standby
Check SR1
1 = Detect locked block
Check SR3
2
1 = Detect V
PP
low
Check SR4
3
1 = Word program error
Standby
Standby
YES
NO
Full Status Register
Check (optional)
NO
YES
PROGRAM
SUSPEND
SR7 = 1
Issue PROGRAM SETUP
Command and
Word Address
Start
Word Program Passed
V
PP
Range Error
Word Program Failed
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
Issue Word Address
and Word Data
PROGRAM
SUSPEND Loop
1
YES
NO
SR1 = 0
YES
NO
SR3 = 0
YES
NO
SR4 = 0
Word Program
Completed
Read Status Register
Bits
PROGRAM Attempted
on a Locked Block