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参数资料
| 型号： | MT28C3224P20 |
| 厂商： | Micron Technology, Inc. |
| 元件分类： | DRAM |
| 英文描述： | FLASH AND SRAM COMBO MEMORY |
| 中文描述： | 闪存和SRAM式内存 |
| 文件页数： | 21/42页 |
| 文件大小： | 498K |
| 代理商： | MT28C3224P20 |
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21
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
READ-WHILE-WRITE/ERASE
CONCURRENCY
It is possible for the device to read from one bank
while erasing/writing to another bank. Once a bank
enters the WRITE/ERASE operation, the other bank
automatically enters read array mode. For example,
during a READ CONCURRENCY operation, if a PRO-
GRAM/ERASE command is issued in bank
a
, then bank
a
changes to the read status mode and bank
b
defaults
to the read array mode. The device reads from bank
b
if
the latched address resides in bank
b
(see Figure 8).
Similarly, if a PROGRAM/ERASE command is issued in
bank
b
, then bank
b
changes to read status mode and
bank
a
defaults to read array mode. When returning to
bank
a
, the device reads program/erase status if the
latched address resides in bank
a
. A correct bank ad-
dress must be specified to read status register after
returning from concurrent read in the other bank.
When reading the CFI or the chip protection regis-
ter, concurrent operation is not allowed on the top boot
device. Concurrent READ of the CFI or the chip protec-
tion register is only allowed when a PROGRAM or ERASE
operation is performed on bank
b
on the bottom boot
device. For a bottom boot device, reading of the CFI
table or the chip protection register is only allowed if
bank
b
is in read array mode. For a top boot device,
reading of the CFI table or the chip protection register
is only allowed if bank
a
is in read array mode.
Figure 8
READ-While-WRITE Concurrency
Bank
a
1 - Erasing/writing to bank
a
2 - Erasing in bank
a
can be
suspended, and a WRITE to
another block in bank
a
can be initiated.
3 - After the WRITE in that block
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
1 - Reading bank
a
Bank
b
1 - Reading from bank
b
1 - Erasing/writing to bank
b
2 - Erasing in bank
b
can be
suspended, and a WRITE to
another block in bank
b
can be initiated.
3 - After the WRITE in that block
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
BLOCK LOCKING
The Flash memory of the MT28C3224P20 and
MT28C3224P18 devices provide a flexible locking
scheme which allows each block to be individually
locked or unlocked with no latency.
The devices offer two-level protection for the blocks.
The first level allows software-only control of block lock-
ing (for data which needs to be changed frequently),
while the second level requires hardware interaction
before locking can be changed (code which does not
require frequent updates).
Control signals F_WP#, DQ0, and DQ1 define the
state of a block; for example, state [001] means F_WP#
= 0, DQ0 = 0 and DQ1 = 1.
Table 8 defines all of the possible locking states.
NOTE:
All blocks are software-locked upon comple-
tion of the power-up sequence.
LOCKED STATE
After a power-up sequence completion, or after a
reset sequence, all blocks are locked (states [001] or
[101]). This means full protection from alteration. Any
PROGRAM or ERASE operations attempted on a locked
block will return an error on bit SR1 of the status regis-
ter. The status of a locked block can be changed to
unlocked or lock down using the appropriate software
commands. Writing the lock command sequence, 60h
followed by 01h, can lock an unlocked block.
UNLOCKED STATE
Unlocked blocks (states [000], [100], [110]) can be
programmed or erased. All unlocked blocks return to
the locked state when the device is reset or powered
down. An unlocked block can be locked or locked down
using the appropriate software command sequence,
60h followed by D0h. (See Table 4.)
LOCKED DOWN STATE
Blocks locked down (state [011]) are protected from
PROGRAM and ERASE operations, but their protection
status cannot be changed using software commands
alone. A locked or unlocked block can be locked down
by writing the lock down command sequence, 60h fol-
lowed by 2Fh. Locked down blocks revert to the locked
state when the device is reset or powered down.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT28C3224P20FL-80 BET | 制造商:Micron Technology Inc 功能描述: |
| MT28C3224P20FL-80 BET TR | 制造商:Micron Technology Inc 功能描述: |
| MT28C6428P18 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:FLASH AND SRAM COMBO MEMORY |
| MT28C6428P18FM-85 BET | 制造商:Micron Technology Inc 功能描述: |
| MT28C6428P18FM-85 BET TR | 制造商:Micron Technology Inc 功能描述: |
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