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参数资料
| 型号： | MT28C3224P20 |
| 厂商： | Micron Technology, Inc. |
| 元件分类： | DRAM |
| 英文描述： | FLASH AND SRAM COMBO MEMORY |
| 中文描述： | 闪存和SRAM式内存 |
| 文件页数： | 12/42页 |
| 文件大小： | 498K |
| 代理商： | MT28C3224P20 |
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F
12
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
Table 5
Command Descriptions
CODE DEVICE MODE
10h
Alt. Program Setup
20h
Erase Setup
BUS CYCLE
First
First
DESCRIPTION
Operates the same as a PROGRAM SETUP command.
Prepares the CSM for an ERASE CONFIRM command. If the next
command is not an ERASE CONFIRM command, the command will
be ignored, and the device will go to read status mode and wait for
another command.
A two-cycle command: The first cycle prepares for a PROGRAM
operation, the second cycle latches addresses and data and initiates
the WSM to execute the program algorithm. The Flash outputs status
register data on the falling edge of F_OE# or F_CE#, whichever
occurs first.
The WSM can set the program status (SR4), and erase status (SR5) bits
in the status register to “1,” but it cannot clear them to “0.” Issuing
this command clears those bits to “0.”
Prepares the CSM for changes to the block locking status. If the next
command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK
DOWN, the command will be ignored, and the device will go to read
status mode.
Places the device into read status register mode. Reading the device
outputs the contents of the status register for the addressed bank.
The device automatically enters this mode for the addressed bank
after a PROGRAM or ERASE operation has been initiated.
Puts the device into the read protection configuration mode so that
reading the device outputs the manufacturer/device codes or block
lock status.
Puts the device into the read query mode so that reading the device
outputs common Flash interface information.
Suspends the currently executing PROGRAM/ERASE operation. The
status register indicates when the operation has been successfully
suspended by setting either the program suspend (SR2) or erase
suspend (SR6) and the WSMS bit (SR7) to a “1” (ready). The WSM
continues to idle in the suspend state, regardless of the state of all
input control pins except F_RP#, which immediately shuts down the
WSM and the remainder of the chip if F_RP# is driven to V
IL
.
Writes a specific code into the device protection register.
40h
Program Setup
First
50h
Clear Status
Register
First
60h
Protection
Configuration
Setup
First
70h
Read Status
Register
First
90h
Read Protection
Configuration
First
98h
Read Query
First
B0h
Program Suspend
First
Erase Suspend
First
C0h
Program Device
Protection Register
Lock Device
Protection Register
First
First
Locks the device protection register; data can no longer be changed.
(continued on the next page)
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相关代理商/技术参数 |
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|---|---|
| MT28C3224P20FL-80 BET | 制造商:Micron Technology Inc 功能描述: |
| MT28C3224P20FL-80 BET TR | 制造商:Micron Technology Inc 功能描述: |
| MT28C6428P18 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:FLASH AND SRAM COMBO MEMORY |
| MT28C6428P18FM-85 BET | 制造商:Micron Technology Inc 功能描述: |
| MT28C6428P18FM-85 BET TR | 制造商:Micron Technology Inc 功能描述: |
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