参数资料
型号: MT46V32M16TG-75ELIT
元件分类: DRAM
英文描述: 32M X 16 DDR DRAM, 0.75 ns, PDSO66
封装: 0.400 INCH, PLASTIC, TSOP-66
文件页数: 18/82页
文件大小: 2855K
代理商: MT46V32M16TG-75ELIT
512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
25
2000 Micron Technology, Inc. All rights reserved.
Figure 16: Random READ Accesses
NOTE:
1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2. Burst length = 2, 4, or 8 (if 4 or 8, the following burst interrupts the previous).
3. n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively.
4. READs are to an active row in any bank.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND
READ
NOP
ADDRESS
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col x
Bank,
Col b
READ
Bank,
Col g
COMMAND
ADDRESS
CL = 2
CK
CK#
COMMAND
ADDRESS
DQ
DQS
CL = 2.5
DQ
DQS
DO
n
DO
x'
DO
g
DO
n'
DO
b
DO
x
DO
b'
DO
n
DO
x'
DO
n'
DO
b
DO
x
DO
b'
T0
T1
T2
T3
T2n
T3n
T4
T5
T4n
T5n
READ
NOP
Bank,
Col n
READ
Bank,
Col g
T0
T1
T2
T3
T2n
T3n
T4
T5
T4n
T5n
DON’T CARE
TRANSITIONING DATA
Bank,
Col x
Bank,
Col b
COMMAND
ADDRESS
CK
CK#
COMMAND
ADDRESS
DQ
DQS
CL = 3
DO
n
DO
x'
DO
n'
DO
b
DO
x
DO
b'
READ
NOP
Bank,
Col n
READ
Bank,
Col g
T0
T1
T2
T3
T3n
T4
T5
T4n
T5n
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