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参数资料
| 型号： | MT46V32M16TG-75ELIT |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件页数： | 50/82页 |
| 文件大小： | 2855K |
| 代理商： | MT46V32M16TG-75ELIT |
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512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
54
2000 Micron Technology, Inc. All rights reserved.
Table 20:
IDD Specifications and Conditions (x16; -5B)
°C
≤ T
A ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
Notes: 1–5, 10, 12, 14, 46; notes appear on page 61–64; See also Table 22, IDD Test Cycle Times, on page 56
PARAMETER/CONDITION
SYMBOL
-5B
UNITS
NOTES
OPERATING CURRENT: One bank; Active-Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per
clock cycle; Address and control inputs changing once every two clock cycles
IDD0
155
mA
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
IDD1
195
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-
down mode; tCK = tCK (MIN); CKE = (LOW)
IDD2P
5mA
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing
once per clock
cycle. VIN = VREF for DQ, DQS, and DM
IDD2F
55
mA
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3P
45
mA
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active
; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
IDD3N
60
mA
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); IOUT = 0mA
IDD4R
210
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W
215
mA
AUTO REFRESH BURST CURRENT:
tREFC =tRC(MIN)
IDD5
345
mA
tREFC = 7.8us,
IDD5A
11
mA
SELF REFRESH CURRENT: CKE
≤ 0.2V
Standard
IDD6
6mA
Low Power (L)
IDD6A
4mA
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed;
tCK = tCK (MIN); Address and control inputs change only during Active READ,
or WRITE commands
IDD7
480
mA
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M16TG-75L | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75Z | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75ZL | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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