- 您现在的位置：买卖IC网 > PDF目录224505 > MT46V32M16TG-75ELIT 32M X 16 DDR DRAM, 0.75 ns, PDSO66 PDF资料下载
参数资料
| 型号： | MT46V32M16TG-75ELIT |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件页数： | 6/82页 |
| 文件大小： | 2855K |
| 代理商： | MT46V32M16TG-75ELIT |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页
512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
14
2000 Micron Technology, Inc. All rights reserved.
NOTE:
1. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
2. For a burst length of two, A1–Ai select the two-
data-element block; A0 selects the first access
within the block.
3. For a burst length of four, A2–Ai select the four-
data-element block; A0–A1 select the first access
within the block.
4. For a burst length of eight, A3–Ai select the eight-
data-element block; A0–A2 select the first access
within the block.
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, 2.5, or 3 (DDR400 only) clocks, as
shown in Figure 8.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 4,
CAS Latency (CL), on page 14 indicates the operating
frequencies at which each CAS latency setting can be
used.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
Figure 8: CAS Latency
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
Table 3:
Burst Definition
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN A
BURST
TYPE=
SEQUENTIAL
TYPE=
INTERLEAVED
2
A0
00-1
0-1
11-0
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Table 4:
CAS Latency (CL)
SPEED
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
CL = 2
CL = 2.5
CL = 3
-5B
75
≤ f ≤ 133
75
≤ f ≤ 167
133
≤ f ≤ 200
-6/-6T
75
≤ f ≤ 133
75
≤ f ≤ 167
-
-75E
75
≤ f ≤ 133
75
≤ f ≤ 133
-
-75Z
75
≤ f ≤ 133
75
≤ f ≤ 133
-
-75
75
≤ f ≤ 100
75
≤ f ≤ 133
-
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ
NOP
READ
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T0
T1
T2
T2n
T3
T3n
T0
T1
T2
T2n
T3
T3n
DON’T CARE
TRANSITIONING DATA
READ
NOP
CK
CK#
COMMAND
DQ
DQS
CL = 3
T0
T1
T2
T3
T3n
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V32M16BN-5BLIT | 32M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| MT46V32M81AZ4-6T:G | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT47H128M8HV-187ELIT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT47H128M8HQ-187ELAT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M16TG-75L | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75Z | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75ZL | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
发布紧急采购，3分钟左右您将得到回复。