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参数资料
| 型号： | MT46V32M16TG-75ELIT |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件页数： | 59/82页 |
| 文件大小： | 2855K |
| 代理商： | MT46V32M16TG-75ELIT |
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512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
62
2000 Micron Technology, Inc. All rights reserved.
progress, DQS could be HIGH during this time,
depending on tDQSS.
22. MIN (tRC or tRFC) for IDD measurements is the
smallest multiple of tCK that meets the minimum
absolute value for the respective parameter. tRAS
(MAX) for IDD measurements is the largest multi-
ple of tCK that meets the maximum absolute
value for tRAS.
23. The refresh period is 64ms. This equates to an
average refresh rate of 7.8125s. However, an
AUTO REFRESH command must be asserted at
least once every 70.3s; burst refreshing or post-
ing by the DRAM controller greater than 8 refresh
cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group
will not differ by more than this maximum
amount for any given device.
25. The data valid window is derived by achieving
other specifications - tHP (tCK/2), tDQSQ, and
tQH (tQH = tHP - tQHS). The data valid window
derates in direct proportion to the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55, because functionality is
uncertain when operating beyond a 45/55 ratio.
The data valid window derating curves are pro-
vided in Figure 35 for duty cycles ranging between
50/50 and 45/55.
26. Referenced to each output group: x4 = DQS with
DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS
with DQ0-DQ7; and UDQS with DQ8-DQ15.
27. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else
CKE is LOW (i.e., during standby).
28. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, VIL(AC)
or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, VIL(DC)
or VIH(DC).
29. The Input capacitance per pin group will not dif-
fer by more than this maximum amount for any
given device.
30. CK and CK# input slew rate must be ≥ 1V/ns
(≥ 2V/ns if measured differentially).
3.750
3.700
3.650
3.600
3.550
3.500
3.450
3.400
3.350
3.300
3.250
3.400
3.350
3.300
3.250
3.200
3.150
3.100
3.050
3.000
2.950
2.900
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Cl o ck Du ty C y c le
ns
—— -75 @ tCK = 10ns
—— -8 @ tCK = 10ns
—— -75 @ tCK = 7.5ns
—— -8 @ tCK = 8ns
Figure 35: Derating Data Valid Window (tQH - tDQSQ)
相关PDF资料 |
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| MT46V32M81AZ4-6T:G | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT47H128M8HV-187ELIT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M16TG-75L | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75Z | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V32M16TG-75ZL | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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