参数资料
型号: MT46V32M16TG-75ELIT
元件分类: DRAM
英文描述: 32M X 16 DDR DRAM, 0.75 ns, PDSO66
封装: 0.400 INCH, PLASTIC, TSOP-66
文件页数: 75/82页
文件大小: 2855K
代理商: MT46V32M16TG-75ELIT
512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
77
2000 Micron Technology, Inc. All rights reserved.
Figure 50: Bank Read - With Auto Precharge
NOTE:
1. DOn = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. The READ command can only be applied at T3 if tRAP is satisfied at T3.
7. tRP starts only after tRAS has been satisfied.
8. Refer to Figure 40 on page 67, Figure 41 on page 68, and Figure 42 on page 69 for detailed DQS and DQ timing.
CK
CK#
CKE
A10
BA0, BA1
tCK
tCH
tCL
tIS
tIH
tIS
tIH
IS
IH
RA
tRC
tRP7
CL = 2
DM
T0
T1
T2
T3
T4
T5
T5n
T6n
T6
T7
T8
DQ1
DQS
Case 1: tAC (MIN) and tDQSCK (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
DQ1
DQS
tRPRE
tRPST
tDQSCK (MIN)
tDQSCK (MAX)
tAC (MIN)
tLZ (MIN)
DO
n
tHZ (MAX)
tAC (MAX)
DO
n
NOP5
COMMAND4
3
ACT
RA
Col n
READ2,6
NOP5
Bank x
RA
Bank x
ACT
Bank x
NOP5
DON’T CARE
TRANSITIONING DATA
tRAS
tLZ(MIN)
tRCD, tRAP6
x8: A12
x16: A11, A12
x4: A0–A9, A11, A12
x8: A0–A9, A11
x16: A0–A9
相关PDF资料
PDF描述
MT46V32M16BN-5BLIT 32M X 16 DDR DRAM, 0.7 ns, PBGA60
MT46V32M81AZ4-6T:G 32M X 4 DDR DRAM, 0.75 ns, PDSO66
MT47H128M8HV-187ELIT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60
MT47H128M8HQ-187ELAT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60
MT48LC2M32B1TG-7 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
相关代理商/技术参数
参数描述
MT46V32M16TG-75L 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM
MT46V32M16TG-75Z 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM
MT46V32M16TG-75ZL 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM