参数资料
型号: MT46V32M81AZ4-6T:G
元件分类: DRAM
英文描述: 32M X 4 DDR DRAM, 0.75 ns, PDSO66
封装: 0.400 INCH, PLASTIC, TSOP-66
文件页数: 40/82页
文件大小: 2866K
128Mb: x4, x8, x16
DDR SDRAM
09005aef8074a655
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MBDDRx4x8x16_2.fm - Rev. J 7/04 EN
45
2000 Micron Technology, Inc. All rights reserved.
This device supports concurrent auto precharge such that when a read with auto precharge
is enabled or a write with auto precharge is enabled any command to other banks is
allowed, as long as that command does not interrupt the read or write data transfer already
in process. In either case, all other related limitations apply (e.g., contention between read
data and write data must be avoided).
3b.
The minimum delay from a read or write command with auto precharge enabled, to a command to
a different bank is summarized below.
NOTE:
CLRU = CAS Latency (CL) rounded up to the next integer
BL = Bust Length
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be
used to end the READ burst prior to asserting a WRITE command.
FROM COMMAND
TO COMMAND
MINIMUM DELAY
(WITH CONCURRENT AUTO PRECHARGE)
WRITE w/AP
READ or READ w/AP
[1 + (BL/2)] * tCK + tWTR
WRITE or WRITE w/AP
(BL/2) * tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK
READ w/AP
READ or READ w/AP
(BL/2) * tCK
WRITE or WRITE w/AP
[CLRU
+ (BL/2)] *tCK
PRECHARGE
1 tCK
ACTIVE
1 tCK
相关PDF资料
PDF描述
MT47H128M8HV-187ELIT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60
MT47H128M8HQ-187ELAT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60
MT48LC2M32B1TG-7 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
MT48LC32M4A2P-7ELIT:G 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
MT55L256L18FT-12TR 256K X 18 ZBT SRAM, 9 ns, PQFP100
相关代理商/技术参数
参数描述
MT46V32M82ZZ5-75 ES 制造商:Micron Technology Inc 功能描述:32MX8 SDRAM DDR PLASTIC PBF FBGA 2.5V - Trays
MT46V32M82ZZ5-75EZ 制造商:Micron Technology Inc 功能描述:32MX8 DDR SDRAM PLASTIC 2.5V - Trays