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参数资料
| 型号： | MT46V32M81AZ4-6T:G |
| 元件分类： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件页数： | 61/82页 |
| 文件大小： | 2866K |
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128Mb: x4, x8, x16
DDR SDRAM
09005aef8074a655
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MBDDRx4x8x16_2.fm - Rev. J 7/04 EN
64
2000 Micron Technology, Inc. All rights reserved.
inner bounding lines of the V-I curve of
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4 for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
Figure 38: Reduced Drive Pull-Down
Characteristics
Figure 39: Reduced Drive Pull-Up
Characteristics
39.
The voltage levels used are derived from a mini-
mum VDD level and the referenced test load. In
practice, the voltage levels obtained from a
properly terminated bus will provide signifi-
cantly different voltage values.
40.
VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a
pulse width ≤ 3ns and the pulse width can not
be greater than 1/3 of the cycle rate. VIL under-
shoot: VIL (MIN) = -1.5V for a pulse width ≤ 3ns
and the pulse width can not be greater than
1/3
of the cycle rate.
41. VDD and VDDQ must track each other.
42. tHZ (MAX) will prevail over tDQSCK (MAX) +
tRPST (MAX) condition. tLZ (MIN) will prevail
over tDQSCK (MIN) + tRPRE (MAX) condition.
43. tRPST end point and tRPRE begin point are not
referenced to a specific voltage level but specify
when the device output is no longer driving
(tRPST), or begins driving (tRPRE).
44. During initialization, VDDQ, VTT, and VREF must be
equal to or less than VDD + 0.3V. Alternatively, VTT
may be 1.35V maximum during power up, even if
VDD/VDDQ are 0V, provided a minimum of 42 of
series resistance is used between the VTT supply
and the input pin.
45. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
46. When an input signal is HIGH or LOW, it is
defined as a steady state logic high or logic low.
47. Random addressing, 50 percent of data changing
at every transfer.
48. Random addressing, 100 percent of data changing
at every transfer.
49. CKE must be active (HIGH) during the entire time
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
tRFC has been satisfied.
50. IDD2N specifies the DQ, DQS and DM to be driven
to a valid high or low logic level. IDD2Q is similar
to IDD2F except IDD2Q specifies the address and
control inputs to remain stable. Although IDD2F,
IDD2N, and IDD2Q are similar, IDD2F is “worst
case.”
51. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset fol-
lowed by 200 clock cycles before any READ com-
mand.
52. This is the DC voltage supplied at the DRAM and
is inclusive of all noise up to 20 MHz. Any noise
above 20 MHz at the DRAM generated from any
source other than that of the DRAM itself may not
exceed the DC voltage range of 2.6V±100mV.
53. The -6/-6T speed grades will operate with
tRAS(min) = 40ns and tRAS(max) = 120,000ns at
any slower frequency.
0
10
20
30
40
50
60
70
80
0.00.5
1.01.5
2.
VOUT (V)
IOU
T
(m
A
)
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
IOU
T
(m
A
)
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相关代理商/技术参数 |
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|---|---|
| MT46V32M82ZZ5-75 ES | 制造商:Micron Technology Inc 功能描述:32MX8 SDRAM DDR PLASTIC PBF FBGA 2.5V - Trays |
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