- 您现在的位置：买卖IC网 > PDF目录224506 > MT46V32M81AZ4-6T:G 32M X 4 DDR DRAM, 0.75 ns, PDSO66 PDF资料下载
参数资料
| 型号： | MT46V32M81AZ4-6T:G |
| 元件分类： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件页数： | 47/82页 |
| 文件大小： | 2866K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页当前第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页
128Mb: x4, x8, x16
DDR SDRAM
09005aef8074a655
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MBDDRx4x8x16_2.fm - Rev. J 7/04 EN
51
2000 Micron Technology, Inc. All rights reserved.
Table 18:
IDD Specifications and Conditions (x4, x8; -5B)
0°C
≤ T
A ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
Notes: 1–5, 10, 12, 14, 46; notes appear on page 61-64; See also Table 23, Idd Test Cycle Times, on page 56
MAX
PARAMETER/CONDITION
SYMBOL
-5B
UNITS
NOTES
OPERATING CURRENT: One bank; Active-Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
IDD0
115
mA
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle
IDD1
135
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDD2P
3
mA
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
tCK = tCK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock
cycle. VIN = VREF for DQ, DQS, and DM
IDD2F
50
mA
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3P
25
mA
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active
; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
IDD3N
50
mA
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN);
IOUT = 0mA
IDD4R
135
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
IDD4W
155
mA
AUTO REFRESH BURST CURRENT:
tREFC =tRC(MIN)
IDD5
240
mA
tREFC = 15.6s
IDD5A
6
mA
SELF REFRESH CURRENT: CKE
≤ 0.2V
Standard
IDD6
4mA
Low Power (L)
IDD6A
1.3
mA
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed;
tCK = tCK (MIN); Address and control inputs change only during
Active READ, or WRITE commands
IDD7
355
mA
相关PDF资料 |
PDF描述 |
|---|---|
| MT47H128M8HV-187ELIT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT47H128M8HQ-187ELAT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| MT48LC32M4A2P-7ELIT:G | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| MT55L256L18FT-12TR | 256K X 18 ZBT SRAM, 9 ns, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V32M82ZZ5-75 ES | 制造商:Micron Technology Inc 功能描述:32MX8 SDRAM DDR PLASTIC PBF FBGA 2.5V - Trays |
| MT46V32M82ZZ5-75EZ | 制造商:Micron Technology Inc 功能描述:32MX8 DDR SDRAM PLASTIC 2.5V - Trays |
发布紧急采购，3分钟左右您将得到回复。