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参数资料
| 型号： | MT46V32M8FG-6TIT:G |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | (8 X 14) MM, PLASTIC, FBGA-60 |
| 文件页数： | 37/93页 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
40
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
44. tRPST end point and tRPRE begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST) or begins driving
(tRPRE).
45. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V.
Alternatively, VTT may be 1.35V maximum during power-up, even if VDD/VDDQ are 0V,
provided a minimum of 42Ω of series resistance is used between the VTT supply and
the input pin.
46. The current Micron part operates below 83 MHz (slowest specified JEDEC operating
frequency). As such, future die may not reflect this option.
47. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
48. Random address is changing; 50% of data is changing at every transfer.
49. Random address is changing; 100% of data is changing at every transfer.
50. CKE must be active (HIGH) during the entire time a REFRESH command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level.
IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
52. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset followed by 200 clock cycles before any READ command.
53. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz.
Any noise above 20 MHz at the DRAM generated from any source other than that of
the DRAM itself may not exceed the DC voltage range of 2.6V ±100mV.
54. The -6/-6T speed grades will operate with tRAS (MIN) = 40ns and
tRAS (MAX) = 120,000ns at any slower frequency.
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