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| 型号： | MT46V32M8FG-6TIT:G |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | (8 X 14) MM, PLASTIC, FBGA-60 |
| 文件页数： | 40/93页 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
43
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Commands
Tables—Table 30 on page 44 and Table 31 on page 45—provide current state/next state
information.
Notes:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A0–An (128Mb: n = 11; 256Mb and 512Mb: n = 12; 1Gb:
n = 13) provide row address.
3. BA0–BA1 provide bank address; A0–Ai provide column address, (where Ai is the most signif-
icant column address bit for a given density and configuration, see Table 2 on page 2) A10
HIGH enables the auto precharge feature (non persistent), and A10 LOW disables the auto
precharge feature.
4. Applies only to READ bursts with auto precharge disabled; this command is undefined (and
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are pre-
charged and BA0–BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing while in self refresh mode, all inputs and
I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0
select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combina-
tions of BA0–BA1 are reserved). A0–An provide the op-code to be written to the selected
mode register.
Table 28:
Truth Table 1 – Commands
CKE is HIGH for all commands shown except SELF REFRESH; All states and sequences not shown are illegal or
reserved
Function
CS#
RAS#
CAS#
WE#
Address
Notes
DESELECT
HX
X
NO OPERATION (NOP)
LH
H
X
ACTIVE (select bank and activate row)
L
H
Bank/row
READ (select bank and column and start READ burst)
L
H
L
H
Bank/col
WRITE (select bank and column and start WRITE burst)
L
H
L
Bank/col
BURST TERMINATE
LH
HL
X
PRECHARGE (deactivate row in bank or banks)
L
H
L
Code
AUTO REFRESH or SELF REFRESH
(enter self refresh mode)
LLL
H
X
LOAD MODE REGISTER
LLLL
Op-code
Table 29:
Truth Table 2 – DM Operation
Used to mask write data, provided coincident with the corresponding data
Name (Function)
DM
DQ
Write enable
L
Valid
Write inhibit
H
X
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参数描述 |
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