参数资料
型号: MT46V32M8FG-6TIT:G
元件分类: DRAM
英文描述: 32M X 8 DDR DRAM, 0.7 ns, PBGA60
封装: (8 X 14) MM, PLASTIC, FBGA-60
文件页数: 68/93页
文件大小: 3632K
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
68
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 33:
READ-to-PRECHARGE
Notes:
1. Provided tRAS (MIN) is met, a READ command with auto precharge enabled would cause a
precharge to be performed at x number of clock cycles after the READ command, where
x =BL/2.
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
assumed that tRAS (MIN) is met.
7. An ACTIVE command to the same bank is only allowed if tRC (MIN) is met.
READ
NOP
PRE
NOP
ACT
Bank a,
Col n
Bank a,
(a or all)
Bank a,
Row
READ
NOP
PRE
NOP
ACT
Bank a,
Col n
CL = 2
tRP
CL = 2.5
DO
n
DO
n
T0
T1
T2
T3
T2n
T3n
T4
T5
T0
T1
T2
T3
T2n
T3n
T4
T5
Bank a,
(a or all)
Bank a,
Row
READ
NOP
PRE
NOP
ACT
Bank a,
Col n
tRP
CL = 3
DO
n
T0
T1
T2
T3
T4n
T3n
T4
T5
Bank a,
(a or all)
Bank a,
Row
Command
Address
DQS
DQ
CK#
CK
Command
Address
DQS
DQ
CK#
CK
Command
Address
DQS
DQ
CK#
CK
Transitioning Data
Don’t Care
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