- 您现在的位置：买卖IC网 > PDF目录229297 > MT46V32M8FG-6TIT:G 32M X 8 DDR DRAM, 0.7 ns, PBGA60 PDF资料下载
参数资料
| 型号： | MT46V32M8FG-6TIT:G |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | (8 X 14) MM, PLASTIC, FBGA-60 |
| 文件页数： | 44/93页 |
| 文件大小： | 3632K |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页当前第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
47
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Commands
Notes:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-
MANDn.
4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay
HIGH until after the read postamble time (tRPST); for a WRITE, CKE must stay HIGH until the
write recovery time (tWR) has been met.
6. Once initialized, including during self refresh mode, VREF must be powered within the spec-
ified range.
7. Upon exit of the self refresh mode, the DLL is automatically enabled. A minimum of 200
clock cycles is needed before applying a READ command for the DLL to lock. DESELECT or
NOP commands should be issued on any clock edges occurring during the tXSNR period.
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in prog-
ress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to
perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents
unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER (LMR)
The mode registers are loaded via inputs A0–An (see "REGISTER DEFINITION" on page
55). The LMR command can only be issued when all banks are idle, and a subsequent
executable command cannot be issued until tMRD is met.
Table 33:
Truth Table 5 – CKE
Notes 1–6 apply to the entire table; Notes appear below
CKEn-1
CKEn
Current State
Commandn
Actionn
Notes
L
Power-down
X
Maintain power-down
Self refresh
X
Maintain self refresh
L
H
Power-down
DESELECT or NOP
Exit power-down
Self refresh
DESELECT or NOP
Exit self refresh
H
L
All banks idle
DESELECT or NOP
Precharge power-down entry
Bank(s) active
DESELECT or NOP
Active power-down entry
All banks idle
AUTO REFRESH
Self refresh entry
H
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V32M8BG-6AT:G | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| M29F800FB55N3E2 | 512K X 16 FLASH 5V PROM, 55 ns, PDSO48 |
| MC12L1NZGF | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
| MD00S1NCQF | ROTARY SWITCH-6POSITIONS, DP6T, LATCHED, 0.25A, 28VDC, THROUGH HOLE-STRAIGHT |
| MD06L1NZGD | ROTARY SWITCH-6POSITIONS, DP6T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
相关代理商/技术参数 |
参数描述 |
|---|
发布紧急采购，3分钟左右您将得到回复。