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参数资料
| 型号： | MT46V32M8FG-6TIT:G |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | (8 X 14) MM, PLASTIC, FBGA-60 |
| 文件页数： | 91/93页 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
89
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
the extended mode register) and NOPs for 200 additional clock cycles before applying a
READ. Any command other than a READ can be performed tXSNR (MIN) after the DLL
reset. NOP or DESELECT commands must be issued during the tXSNR (MIN) time.
Self refresh is not supported on automotive tempature (AT) devices.
Figure 54:
Self Refresh Mode
Notes:
1. Clock must be stable until after the SELF REFRESH command has been registered. A change
in clock frequency is allowed before Ta0, provided it is within the specified tCK limits.
Regardless, the clock must be stable before exiting self refresh mode—that is, the clock
must be cycling within specifications by Ta0.
2. NOPs are interchangeable with DESELECT commands.
3. AUTO REFRESH is not required at this point but is highly recommended.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5. tXSNR is required before any non-READ command can be applied; that is only NOP or DESE-
LECT commands are allowed until Tb1.
6. tXSRD (200 cycles of a valid clock with CKE = HIGH) is required before any READ command
can be applied.
7. As a general rule, any time self refresh mode is exited, the DRAM may not re-enter the self
refresh mode until all rows have been refreshed via the AUTO REFRESH command at the
distributed refresh rate, tREFI, or faster. However, the self refresh mode may be re-entered
anytime after exiting if each of the following conditions is met:
7a. The DRAM had been in the self refresh mode for a minimum of 200ms prior to exiting.
7b. tXSNR and tXSRD are not violated.
7c. At least two AUTO REFRESH commands are performed during each tREFI interval while
the DRAM remains out of self refresh mode.
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.
9. Once the device is initialized, VREF must always be powered within specified range.
CK1
CK#
Command2
NOP
AR
Address
CKE
DQ
DM
DQS
NOP
tRP4
tCH
tCL
tCK
tIS
tIH
tIS
tIH
t IS
Enter self refresh mode7
Exit self refresh mode7
T0
T11
Ta1
Don’t Care
Ta01
tXSRD6
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相关代理商/技术参数 |
参数描述 |
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