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参数资料
| 型号： | MT46V32M8FG-6TIT:G |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | (8 X 14) MM, PLASTIC, FBGA-60 |
| 文件页数： | 90/93页 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
88
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
Although not a JEDEC requirement, to provide for future functionality features, CKE
must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered and ends tRFC later.
Figure 53:
Auto Refresh Mode
Notes:
1. NOP commands are shown for ease of illustration; other valid commands may be possible at
these times. CKE must be active during clock-positive transitions.
2. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time; CKE must
be active during clock-positive transitions.
3. The second AUTO REFRESH is not required and is only shown as an example of two back-to-
back AUTO REFRESH commands.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
(that is, must precharge all active banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for the operations shown.
SELF REFRESH
When in the self refresh mode, the DDR SDRAM retains data without external clocking.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled upon exiting SELF REFRESH (a DLL reset and 200 clock cycles must then occur
before a READ command can be issued). Input signals except CKE are “Don’t Care”
during SELF REFRESH. VREF voltage is also required for the full duration of SELF
REFRESH.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK
and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for tXSNR because time is required for the
completion of any internal refresh in progress. A simple algorithm for meeting both
refresh and DLL requirements is to apply NOPs for tXSRD time, then a DLL RESET (via
CK
CK#
Command
NOP1
Valid
NOP1
PRE
CKE
RA
Address
A10
BA0, BA1
Bank(s)4
BA
AR
NOP1,2
AR3
NOP1,2
ACT
NOP1
One bank
All banks
CK
tCH
tCL
tIS
tIH
tIS tIH
RA
DQ
5
DM
5
DQS
5
tRFC
tRP
tRFC
T0
T1
T2
T3
T4
Ta0
Tb0
Ta1
Tb1Tb2
Don’t Care
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