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参数资料
| 型号： | MT46V64M4 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4组,双数据速率同步动态RAM) |
| 中文描述： | 16梅格× 4 × 4银行DDR SDRAM内存（1,600 × 4 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 12/69页 |
| 文件大小： | 2410K |
| 代理商： | MT46V64M4 |
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12
256Mb: x4, x8, x16 DDR SDRAM
256Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR SDRAM
ADVANCE
Figure 3
Extended Mode Register Definition
EXTENDED MODE REGISTER
The extended mode register controls functions be-
yond those controlled by the mode register; these addi-
tional functions are DLL enable/disable, output drive
strength, and QFC#. These functions are controlled via
the bits shown in Figure 3. The extended mode register
is programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The enabling
of the DLL should always be followed by a LOAD
MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecified operation.
Output Drive Strength
The normal drive strength for all outputs are speci-
fied to be SSTL2, Class II. The x16 supports an option for
reduced drive. This option is intended for the support of
the lighter load and/or point-to-point environments.
The selection of the reduced drive strength will alter the
DQs and DQSs from SSTL2, Class II drive strength to a
reduced drive strength, which is approximately 54% of
the SSTL2, Class II drive strength. Micron will support
these x16 options: 1) Full drive strength only (not
programmable); 2) Reduced drive strength only (not
programable); and 3) Programmable full or reduced
drive strength.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL
enable is required during power-up initialization and
upon returning to normal operation after having dis-
abled the DLL for the purpose of debug or evaluation.
(When the device exits self refresh mode, the DLL is
enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
Operating Mode
Reserved
Reserved
Valid
–
0
–
0
–
0
1
DLL
Enable
Disable
DLL
01
11
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
E0
0
1
Drive Strength
Normal
Reduced
E12
0
–
QFC Function
Disabled
Reserved
E2
3
E0
E1,
Operating Mode
A10
A11
A12
BA0BA1
10
11
12
13
14
NOTE:
1. E14 and E13 (BA0 and BA1) must be
“
1, 0
”
to select the
Extended Mode Register (vs. the base Mode Register).
2. The reduced drive strength option is not supported on
the x4 and x8 versions: and is only available on the D3 version
of the x16 device.
3. The QFC# option is not supported.
E2,
E3
E4
0
–
0
–
0
–
0
–
0
–
E6 E5
E7
E8
E9
0
–
0
–
E10
E11
0
–
E12
DS
QFC
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相关代理商/技术参数 |
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|---|---|
| MT46V64M4_1 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Double Data Rate (DDR) SDRAM |
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