65
256Mb: x4, x8, x16 DDR SDRAM
256Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR SDRAM
ADVANCE
BANK READ – WITH AUTO PRECHARGE
CK
CK#
CKE
A10
BA0, BA1
t
CK
t
CH
t
CL
t
IS
t
IS
t
IH
t
IS
t
IS
t
IH
t
IH
t
IH
IS
IH
RA
t
RC
t
RP
CL = 2
DM
T0
T1
T2
T3
T4
T5
T5n
T6n
T6
T7
T8
DQ
1
DQS
Case 1:
t
AC
MIN
and
t
DQSCK
MIN
Case 2:
t
AC
(
MAX)
and
t
DQSCK
(
MAX)
DQ
1
DQS
t
RPRE
t
RPRE
t
RPST
t
RPST
t
DQSCK
(
MIN)
t
DQSCK
(
MAX)
t
AC
(
MIN)
t
LZ
(
MIN)
DO
n
t
HZ
(
MAX)
t
AC
(
MAX)
t
LZ
(
MAX)
DO
n
NOP5
NOP5
COMMAND
4
3
ACT
RA
RA
Col
n
READ2,6
NOP5
Bank
x
RA
RA
RA
Bank
x
ACT
Bank
x
NOP5
NOP5
NOP5
t
HZ
(
MIN)
NOTE:
1. DO
n
= data-out from column
n;
subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = Row Address, BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. The READ command can only be applied at T3 if
t
RAP is satisfied at T3
7. Refer to figure 27, 27A, and 28 for detailed DQS and DQ timing.
DON
’
T CARE
TRANSITIONING DATA
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
x4: A12
x8: A11, A12
x16: A9, A11, A12
t
RAS
t
LZ
(
MIN)
t
LZ
(
MAX)
t
RCD,
t
RAP6