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参数资料
| 型号： | MT46V64M4 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4组,双数据速率同步动态RAM) |
| 中文描述： | 16梅格× 4 × 4银行DDR SDRAM内存（1,600 × 4 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 39/69页 |
| 文件大小： | 2410K |
| 代理商： | MT46V64M4 |
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39
256Mb: x4, x8, x16 DDR SDRAM
256Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR SDRAM
ADVANCE
TRUTH TABLE 3 – CURRENT STATE BANK
n
- COMMAND TO BANK
n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RA S#CA S# WE#
Any
H
L
L
Idle
L
L
L
Row Active
L
L
Read
L
(Auto-
L
Precharge
L
Disabled)
L
Write
L
(Auto-
L
Precharge
L
Disabled)
COMMA ND/A CTION
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
NOTES
X
H
L
L
L
H
H
L
H
H
L
H
H
H
L
X
H
H
L
L
L
L
H
L
L
H
H
L
L
H
X
H
H
H
L
H
L
L
H
L
L
L
H
L
L
7
7
10
10
8
10
10, 12
8
9
10, 11
10
8, 11
NOTE:
1. This table applies when CKE
n-1
was HIGH and CKE
n
is HIGH (see Truth Table 2) and after
t
XSNR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the com-
mands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in
the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and
t
RP has been met.
Row Active: A row in the bank has been activated, and
t
RCD has been met. No data bursts/accesses
and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT
or NOP commands, or allowable commands to the other bank should be issued on any clock edge occur-
ring during these states. Allowable commands to the other bank are determined by its current state and
Truth Table 3, and according to Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when
t
RP is met. Once
t
RP is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when
t
RCD is met.
Once
t
RCD is met, the bank will be in the
“
row active
”
state.
Read w/Auto-
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends
when
t
RP has been met. Once
t
RP is met, the bank will be in the idle state.
Write w/Auto-
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends
when
t
RP has been met. Once
t
RP is met, the bank will be in the idle state.
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V64M8 | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) |
| MT48LC16M8A1TG | SYNCHRONOUS DRAM |
| MT48LC32M4A1 | ECONOLINE: RSZ/P - 1kVDC |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V64M4_1 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Double Data Rate (DDR) SDRAM |
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