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参数资料
| 型号： | MT46V64M4 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4组,双数据速率同步动态RAM) |
| 中文描述： | 16梅格× 4 × 4银行DDR SDRAM内存（1,600 × 4 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 9/69页 |
| 文件大小： | 2410K |
| 代理商： | MT46V64M4 |
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9
256Mb: x4, x8, x16 DDR SDRAM
256Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR SDRAM
ADVANCE
FUNCTIONAL DESCRIPTION
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
268,435,456 bits. The 256Mb DDR SDRAM is internally
configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2
n
-prefetch archi-
tecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for the 256Mb DDR SDRAM consists of a
single 2
n
-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding
n
-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registration
of an ACTIVE command, which is then followed by a
READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A12 select the row). The address bits regis-
tered coincident with the READ or WRITE command
are used to select the starting column location for the
burst access.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed in-
formation covering device initialization, register defini-
tion, command descriptions and device operation.
Initialization
DDR SDRAMs must be powered up and initialized in
a predefined manner. Operational procedures other
than those specified may result in undefined operation.
Power must first be applied to V
DD
and V
DD
Q simulta-
neously, and then to V
REF
(and to the system V
TT
). V
TT
must be applied after V
DD
Q to avoid device latch-up,
which may cause permanent damage to the device. V
REF
can be applied any time after V
DD
Q but is expected to be
nominally coincident with V
TT
. Except for CKE, inputs
are not recognized as valid until after V
REF
is applied.
CKE is an SSTL_2 input but will detect an LVCMOS LOW
level after V
DD
is applied. Maintaining an LVCMOS
LOW level on CKE during power-up is required to ensure
that the DQ and DQS outputs will be in the High-Z state,
where they will remain until driven in normal operation
(by a read access). After all power supply and reference
voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200μs delay prior to applying an
executable command.
Once the 200μs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 HIGH and BA0 LOW)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operat-
ing parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed (
t
RFC must be satisfied.) Addition-
ally, a LOAD MODE REGISTER command for the mode
register with the reset DLL bit deactivated (i.e., to pro-
gram operating parameters without resetting the DLL)
is required. Following these requirements, the DDR
SDRAM is ready for normal operation.
Register Definition
MODE REGISTER
The mode register is used to define the specific mode
of operation of the DDR SDRAM. This definition in-
cludes the selection of a burst length, a burst type, a CAS
latency and an operating mode, as shown in Figure 1.
The mode register is programmed via the MODE REGIS-
TER SET command (with BA0 = 0 and BA1 = 0) and will
retain the stored information until it is programmed
again or the device loses power (except for bit A8, which
is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all banks are idle and no bursts are in progress, and
the controller must wait the specified time before initi-
ating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved), A4-
A6 specify the CAS latency, and A7-A12 specify the
operating mode.
Burst Length
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable, as
shown in Figure 1. The burst length determines the
maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V64M4_1 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Double Data Rate (DDR) SDRAM |
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