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参数资料
| 型号： | MT46V64M4 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4组,双数据速率同步动态RAM) |
| 中文描述： | 16梅格× 4 × 4银行DDR SDRAM内存（1,600 × 4 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 2/69页 |
| 文件大小： | 2410K |
| 代理商： | MT46V64M4 |
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256Mb: x4, x8, x16 DDR SDRAM
256Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR SDRAM
ADVANCE
GENERAL DESCRIPTION
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-
bank DRAM.
The 256Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2
n
-prefetch archi-
tecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for the 256Mb DDR SDRAM effectively
consists of a single 2
n
-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two correspond-
ing
n
-bit wide, one-half-clock-cycle data transfers at the
I/O pins.
A bidirectional data strobe (DQS) is transmitted ex-
ternally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR SDRAM
during READs and by the memory controller during
WRITEs. DQS is edge-aligned with data for READs and
center-aligned with data for WRITEs. The x16 offering
has two data strobes, one for the lower byte and one for
the upper byte.
The 256Mb DDR SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH and
CK# going LOW will be referred to as the positive edge
of CK. Commands (address and control signals) are
registered at every positive edge of CK. Input data is
registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or
WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4 or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for con-
current operation, thereby providing high effective band-
width by hiding row precharge and activation time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All full
drive option outputs are SSTL_2, Class II compatible.
NOTE:
1. The functionality and the timing specifications
discussed in this data sheet are for the DLL-
enabled mode of operation.
2. Throughout the data sheet, the various figures and
text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise.
Additionally, the x16 is divided in to two bytes –
the lower byte and upper byte. For the lower byte
(DQ0 through DQ7) DM refers to LDM and DQS
refers to LDQS; and for the upper byte (DQ8
through DQ15) DM refers to UDM and DQS refers
to UDQS.
PART NUMBER
MT46V64M4TG-xx
MT46V64M4TG-xxL
CONFIGURATION
64 Meg x 4
64 Meg x 4
I/O DRIVE LEVEL
Full Drive
Full Drive
REFRESH OPTION
Standard
Low Power
MT46V32M8TG-xx
MT46V32M8TG-xxL
32 Meg x 8
32 Meg x 8
Full Drive
Full Drive
Standard
Low Power
MT46V16M16D1TG-xx
MT46V16M16D1TG-xxL
MT46V16M16D2TG-xx
MT46V16M16D2TG-xxL
MT46V16M16D3TG-xx
MT46V16M16D3TG-xxL
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
Full Drive
Full Drive
Reduced Drive
Reduced Drive
Programmable Drive
Programmable Drive
Standard
Low Power
Standard
Low Power
Standard
Low Power
(Note: xx= 7, 75, or 8)
256MB DDR SDRAM PART NUMBERS
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V64M8 | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) |
| MT48LC16M8A1TG | SYNCHRONOUS DRAM |
| MT48LC32M4A1 | ECONOLINE: RSZ/P - 1kVDC |
| MT48LC32M4A2 | SYNCHRONOUS DRAM |
| MT48LC32M4A1TG | SYNCHRONOUS DRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V64M4_1 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Double Data Rate (DDR) SDRAM |
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