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| 型号： | MT46V64M4 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4组,双数据速率同步动态RAM) |
| 中文描述： | 16梅格× 4 × 4银行DDR SDRAM内存（1,600 × 4 × 4组，双数据速率同步动态RAM）的 |
| 文件页数： | 50/69页 |
| 文件大小： | 2410K |
| 代理商： | MT46V64M4 |
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50
256Mb: x4, x8, x16 DDR SDRAM
256Mx4x8x16DDR_B.p65
–
Rev. B; Pub. 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR SDRAM
ADVANCE
4.
AC timing and I
DD
tests may use a V
IL
-to-V
IH
swing of up to 1.5V in the test environment, but
input timing is still referenced to V
REF
(or to the
crossing point for CK/CK#), and parameter
specifications are guaranteed for the specified AC
input levels under normal use conditions. The
minimum slew rate for the input signals used to
test the device is 1V/ns in the range between
V
IL
(
AC
) and V
IH
(
AC
).
The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in
that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
V
REF
is expected to equal V
DD
Q/2 of the transmit-
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V
REF
may not exceed ±2 percent of the
DC value. Thus, from V
DD
Q/2, V
REF
is allowed
±25mV for DC error and an additional ±25mV
for AC noise.
V
TT
is not applied directly to the device. V
TT
is a
system supply for signal termination resistors, is
expected to be set equal to V
REF
and must track
variations in the DC level of V
REF
.
V
ID
is the magnitude of the difference between the
input level on CK and the input level on CK#.
The value of V
IX
is expected to equal V
DD
Q/2 of
the transmitting device and must track variations
in the DC level of the same.
10. I
DD
is dependent on output loading and cycle
rates. Specified values are obtained with minimum
cycle time at CL = 2 for -7 and -8, CL = 2.5 for
-75 with the outputs open.
11. Enables on-chip refresh and address counters.
5.
6.
7.
8.
9.
NOTES
1.
All voltages referenced to V
SS
.
2.
Tests for AC timing, I
DD
, and electrical AC and
DC characteristics may be conducted at nominal
reference/supply voltage levels, but the related
specifications and device operation are guaran-
teed for the full voltage range specified.
3.
Outputs measured with equivalent load:
12. I
DD
specifications are tested after the device is
properly initialized, and is averaged at the
defined cycle rate.
13. This parameter is sampled. V
DD
= +2.5V ±0.2V,
V
DD
Q = +2.5V ±0.2V, V
REF
= V
SS
, f = 100 MHz,
T
A
= 25°C, V
OUT
(
DC
) = V
DD
Q/2, V
OUT
(peak to
peak) = 0.2V. DM input is grouped with I/O pins,
reflecting the fact that they are matched in
loading.
14. Command/Address input slew rate = 0.5V/ns.
For -7 and -75 with slew rates 1V/ns and faster,
t
IS and
t
IH are reduced to 900ps. If the slew rate
is less than 0.5V/ns, timing must be derated:
t
IS has an additional 50ps per each 100mV/ns
reduction in slew rate from the 500mV/ns.
t
IH has 0ps added, that is, it remains constant.
If the slew rate exceeds 4.5V/ns, functionality is
uncertain.
15. The CK/CK# input reference level (for timing
referenced to CK/CK#) is the point at which CK
and CK# cross; the input reference level for signals
other than CK/CK# is V
REF
.
16. Inputs are not recognized as valid until V
REF
stabilizes. Exception: during the period before
V
REF
stabilizes, CKE
≤
0.3 x V
DD
Q is recognized as
LOW.
17. The output timing reference level, as measured at
the timing reference point indicated in Note 3, is
V
TT
.
18.
t
HZ and
t
LZ transitions occur in the same access
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
19. The maximum limit for this parameter is not a
device limit. The device will operate with a greater
value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
20. This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
t
DQSS.
22. MIN (
t
RC or
t
RFC) for I
DD
measurements is the
smallest multiple of
t
CK that meets the minimum
absolute value for the respective parameter.
t
RAS
(MAX) for I
DD
measurements is the largest
multiple of
t
CK that meets the maximum
absolute value for
t
RAS.
Output
(V
OUT
)
Reference
Point
30pF
50
V
TT
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相关代理商/技术参数 |
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|---|---|
| MT46V64M4_1 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:Double Data Rate (DDR) SDRAM |
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