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参数资料
| 型号： | NAND01GW3B2AN6F |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 128M X 8 FLASH 3V PROM, 25000 ns, PDSO48 |
| 封装： | 12 X 20 MM, LEAD FREE, PLASTIC, TSOP-48 |
| 文件页数： | 27/64页 |
| 文件大小： | 632K |
| 代理商： | NAND01GW3B2AN6F |
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NAND01G-B, NAND02G-B
Device operations
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6.8
Read Status Register
The device contains a Status Register which provides information on the current or previous
Program or Erase operation. The various bits in the Status Register convey information and
errors on the operation.
The Status Register is read by issuing the Read Status Register command. The Status
Register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the Status
Register.
After the Read Status Register command has been issued, the device remains in Read
Status Register mode until another command is issued. Therefore if a Read Status Register
command is issued during a Random Read cycle a new Read command must be issued to
continue with a Page Read operation.
The Status Register bits are summarized in Table 13: Status Register Bits,. Refer to
Table 13 in conjunction with the following text descriptions.
6.8.1
Write Protection Bit (SR7)
The Write Protection bit can be used to identify if the device is protected or not. If the Write
Protection bit is set to ‘1’ the device is not protected and program or erase operations are
allowed. If the Write Protection bit is set to ‘0’ the device is protected and program or erase
operations are not allowed.
6.8.2
P/E/R Controller and Cache Ready/Busy Bit (SR6)
Status Register bit SR6 has two different functions depending on the current operation.
During Cache Program operations SR6 acts as a Cache Program Ready/Busy bit, which
indicates whether the Cache Register is ready to accept new data. When SR6 is set to '0',
the Cache Register is busy and when SR6 is set to '1', the Cache Register is ready to
accept new data.
During all other operations SR6 acts as a P/E/R Controller bit, which indicates whether the
P/E/R Controller is active or inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R
Controller is active (device is busy); when the bit is set to ‘1’, the P/E/R Controller is inactive
(device is ready).
6.8.3
P/E/R Controller Bit (SR5)
The Program/Erase/Read Controller bit indicates whether the P/E/R Controller is active or
inactive. When the P/E/R Controller bit is set to ‘0’, the P/E/R Controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R Controller is inactive (device is ready).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NAND01GW3B2AN6T | 功能描述:闪存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| NAND01GW3B2AZA1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory |
| NAND01GW3B2AZA6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory |
| NAND01GW3B2AZA6E | 功能描述:闪存 NAND MEDIA FLASH RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| NAND01GW3B2AZA6F | 制造商:Micron Technology Inc 功能描述:FLASH PARALLEL 3.3V 1GBIT 128MX8 25US 63VFBGA - Tape and Reel |
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