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| 型号： | OR4E041BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 110/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E041BM680-DB |
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Lattice Semiconductor
61
Data Sheet
September, 2002
ORCA Series 4 FPGAs
FPGA States of Operation (continued)
Reconguration
To recongure the FPGA when the device is operating
in the system, a low pulse is input into PRGM or one of
the program bits in the embedded system bus control
register must be set. The conguration data in the
FPGA is cleared, and the I/Os not used for congura-
tion are 3-stated with a pullup. The FPGA then samples
the mode select inputs and begins reconguration.
When reconguration is complete, DONE is released,
allowing it to be pulled high.
Partial Reconguration
All ORCA device families have been designed to allow
a partial reconguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
conguration sequence that tells the FPGA to not reset
all of the conguration RAM during a reconguration.
Then only the conguration frames that are to be modi-
ed need to be rewritten, thereby reducing the congu-
ration time.
Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial reconguration is being done. If this is done, the
user must be careful to not cause contention between
the two congurations (the bit stream resident in the
FPGA and the partial reconguration bit stream) as the
second reconguration bit stream is being loaded.
During a partial re-conguration where the congura-
tion option is set to have the internal logic remain active
during conguration the internal SLJC BIDI signals will
always be 3-stated. Previous families of ORCA FPGAs
would allow the BIDIs to continue to be under user
logic control during a partial re-conguration.
Other Conguration Options
There are many other conguration options available to
the user that can be set during bit stream generation in
ORCA Foundry. These include options to enable
boundary-scan and/or the MPI and/or the programma-
ble PLL blocks, readback options, and options to con-
trol and use the internal oscillator after conguration.
Other useful options that affect the next conguration
(not the current conguration process) include options
to disable the global set/reset during conguration, dis-
able the 3-state of I/Os during conguration, and dis-
able the reset of internal RAMs during conguration to
allow for partial congurations (see above). For more
information on how to set these and other conguration
options, please see the ORCA Foundry documenta-
tion.
Conguration Data Format
The ORCA Foundry Development System interfaces
with front-end design entry tools and provides tools to
produce a fully congured FPGA. This section dis-
cusses using the ORCA Foundry Development System
to generate conguration RAM data and then provides
the details of the conguration frame format.
Using ORCA Foundry to Generate Congu-
ration RAM Data
The conguration data bit stream denes the I/O func-
tionality, logic, and interconnections within the FPGA.
The bit stream is generated by the development sys-
tem. The bit stream created by the bit stream genera-
tion tool is a series of 1s and 0s used to write the FPGA
conguration RAM. It can be loaded into the FPGA
using one of the conguration modes discussed later.
In bit stream generator, the designer selects options
that affect the FPGA’s functionality. Using the output of
the bit stream generator, circuit_name.bit, the devel-
opment system’s download tool can load the congura-
tion data into the ORCA series FPGA evaluation board
from a PC or workstation.
A download cable that can be used to download from
any PC or workstation supported by ORCA Foundry is
available. This cable allows download to an FPGA that
can be programmed via the serial conguration inter-
face (requiring the mode pins to be set) or the JTAG
boundary scan interface (not requiring the setting of
mode pins). The lead device can then program other
FPGAs or FPSCs on the board via daisy-chaining.
Alternatively, a user can program a PROM (such as a
Serial ROM or a standard EPROM) and load the FPGA
from the PROM. The development system’s PROM
programming tool produces a le in .mcs, .tek or .exo
format.
相关PDF资料 |
PDF描述 |
|---|---|
| OR4E042BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E042BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E042BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E043BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E043BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BA352C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BA352I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BM416C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BM416I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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