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| 型号： | OR4E041BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 78/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E041BM680-DB |
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32
Lattice Semiconductor
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Routing Resources (continued)
Cycle Stealing
A new feature in Series 4 FPGAs is the ability to steal
time from one register-to-register path and use that
time in either the previous path before the rst register
or in a later path after the last register. This is done
through selectable clock delays for every PLC register,
EBR register, and PIO register. There are four pro-
grammable delay settings, including the default zero
added delay value. This allows performance increases
on typical critical paths from 15% to 40%. ORCA
Foundry 2001 and later include software to automati-
cally take advantage of this capability to increase over-
all system speed. This is done after place and route is
completed and uses timing driven algorithms based on
the customer’s preference le. A hold time check is
also performed to verify no minimum hold time issues
are introduced. More information on this clocking fea-
ture, including how it can be used to improve device
setup times, hold times, clock-to-out delays and can
reduce ground bounce caused by switching outputs
can be found in the Cycle Stealing application note.
Programmable Input/Output Cells (PIC)
Programmable I/O
The Series 4 programmable I/O addresses the demand
for the exibility to select I/O that meets system inter-
face requirements. I/Os can be programmed in the
same manner as in previous ORCA devices with the
addition of new features which allow the user the exi-
bility to select new I/O types that support high-speed
interfaces.
Each PIC contains up to four programmable I/O (PIO)
pads and are interfaced through a common interface
block (CIB) to the FPGA array. The PIC is split into two
pairs of I/O pads with each pair having independent
clocks, clock enables, local set/reset, and global
set/reset enable/disable.
On the input side, each PIO contains a programmable
latch/FF which enables very fast latching of data from
any pad. The combination provides for very low setup
requirements and zero hold times for signals coming
on-chip. It may also be used to demultiplex an input sig-
nal, such as a multiplexed address/data signal, and
register the signals without explicitly building a demulti-
plexer with a PFU.
On the output side of each PIO, an output from the PLC
array can be routed to each output FF, and logic can be
associated with each I/O pad. The output logic associ-
ated with each pad allows for multiplexing of output sig-
nals and other functions of two output signals.
The output FF, in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The out-
put buffer signal can be inverted, and the 3-state con-
trol can be made active-high, active-low, or always
enabled. In addition, this 3-state signal can be regis-
tered or nonregistered.
The Series 4 I/O logic has been enhanced to include
modes for high-speed uplink and downlink capabilities.
These modes are supported through shift register logic
which divides down incoming data or multiplies up out-
going data. This new logic block also supports high-
speed DDR mode requirements where data is clocked
into and out of the I/O buffers on both edges of the
clock.
The new programmable I/O cell allows designers to
select I/Os which meet many new communication stan-
dards permitting the device to hook up directly without
any external interface translation. They support tradi-
tional FPGA standards as well as high-speed single-
ended and differential pair signaling (as shown in
Table 13). Based on a programmable, bank-oriented
I/O ring architecture, designs can be implemented
using 3.3 V, 2.5 V, 1.8 V, and 1.5 V I/O levels.
The I/O on the OR4Exxx Series devices allows compli-
ance with PCI local bus (Rev. 2.2) 3.3 V signaling envi-
ronments. The signaling environment used for each
input buffer can be selected on a per-pin basis. The
selection provides the appropriate I/O clamping diodes
for PCI compliance.
More information on the Series 4 programmable I/O
structure is available in the various application notes.
相关PDF资料 |
PDF描述 |
|---|---|
| OR4E042BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E042BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E042BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E043BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E043BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BA352C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BA352I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BM416C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BM416I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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