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| 型号： | OR4E041BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 77/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E041BM680-DB |
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Lattice Semiconductor
31
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Routing Resources
The abundant routing resources of the Series 4 archi-
tecture are organized to route signals individually or as
buses with related control signals. Both local and glo-
bal signals utilize high-speed buffered and nonbuffered
routes. One PLC segmented (x1), six PLC segmented
(x6), and bused half chip (xHL) routes are patterned
together to provide high connectivity with fast software
routing times and high-speed system performance.
x1 routes cross width of one PLC and provide local
connectivity to PFU and SLIC inputs and outputs. x6
lines cross width of 6 PLCs and are unidirectional and
buffered with taps in the middle and on the end. Seg-
ments allow connectivity to PFU/SLIC outputs (driven
at one end-point), other x6 lines (at end-points), and
x1 lines for access to PFU/SLIC inputs. xH lines run
vertically and horizontally the distance of half the
device and are useful for driving medium/long distance
3-state routing.
The improved routing resources offer great exibility in
moving signals to and from the logic core. This exibil-
ity translates into an improved capability to route
designs at the required speeds even when the I/O sig-
nals have been locked to specic pins. The buffered
routing capability also allows a very large fanout to be
driven from each logic output, thus greatly reducing the
amount of logic replication required by synthetic tools.
Generally, the ORCA Foundry Development System is
used to automatically route interconnections. Interac-
tive routing with the ORCA Foundry design editor
(EPIC) is also available for design optimization.
The routing resources consist of switching circuitry and
metal interconnect segments. Generally, the metal
lines which carry the signals are designated as routing
segments. The switching circuitry connects the routing
segments, providing one or more of three basic func-
tions: signal switching, amplication, and isolation. A
net running from a PFU, EBR, or PIO output (source) to
a PLC, EBR, or PIO input (destination) consists of one
or more routing segments, connected by switching cir-
cuitry called congurable interconnect points (CIPs).
Clock Distribution Network
Clock distribution is made up of three types of clock
networks: primary, secondary, and edge clocks. these
are described below and more information is available
in the Series 4 Clocking Strategies application note.
Global Primary Clock Nets
The Series 4 FPGAs provide eight fully distributed glo-
bal primary clock net routing resources. The scheme
dedicates four of the eight resources to provide fast pri-
mary nets and four are available for general primary
nets. The fast primary nets are targeted toward low-
skew and small injection times while the general pri-
mary nets are also targeted toward low-skew but have
more source connection exibility. Fast access to the
global primary nets can be sourced from two pairs of
pads located in the center of each side of the device,
from the programmable PLLs and dedicated network
PLLs located in the corners, or from general routing at
the center of the device or at the middle of any side of
the device. The I/O pads are semi-dedicated in pairs for
use of differential I/O clocking or single-ended I/O clock
sources. However if these pads are not needed to
source the clock network they can be utilized for gen-
eral I/O. The clock routing scheme is patterned using
vertical and horizontal routes which provide connectiv-
ity to all PLC columns.
Secondary Clock and Control Nets
Secondary clock control and routing provides exible
clocking and control signalling for local regions. Since
secondary nets usually have high fanouts and require
low skew, the Series 4 devices utilize a spine and
branch that uses x6 segments with high-speed connec-
tions provided from the spines to the branches. The
branches then have high-speed connections to PLC,
PIO, and EBR clock and control signals. This strategy
provides a exible connectivity and routes can be
sourced from any I/O pin, all PLLs, or from PLC or EBR
logic.
Secondary Edge Clock Nets and Fast Edge
Clock Nets
Six secondary edge clock nets per side are distributed
around the edges of the device and are available for
every PIO. All PIOs and PLLs can drive the secondary
edge clocks and are used in conjunction with the sec-
ondary spines discussed above to drive the same edge
clock signal into the internal logic array. The edge sec-
ondary clocks provide fast injection to the PLC array
and I/O registers. One of the six secondary edge
clocks provided per side of the device is a special fast
edge clock net that only clocks input registers for fur-
ther reduced setup/hold times.This timing path can only
be driven from one of the four PIO input pins in each
PIC.
相关PDF资料 |
PDF描述 |
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| OR4E042BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E042BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E042BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E043BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E043BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BA352C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BA352I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BM416C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BM416I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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