参数资料
型号: OR4E041BM680-DB
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
英文描述: FPGA, 1296 CLBS, 380000 GATES, PBGA680
封装: PLASTIC, FBGA-680
文件页数: 72/151页
文件大小: 2680K
代理商: OR4E041BM680-DB
Lattice Semiconductor
27
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Embedded Block RAM (EBR) (continued)
FIFO Modes
FIFOs can be congured to 256, 512, or 1K depths and
36, 18, or 9 widths respectively but also can be
expanded using multiple blocks. FIFO works synchro-
nously with the same read and write clock where the
read port can be registered on the output or not regis-
tered. It can also be optionally congured asynchro-
nously with different read and write clocks and the
same read port register options.
Integrated ags allow the user the ability to fully utilize
the EBR for FIFO, without the need to dedicate an
address for providing distinct full/empty status. There
are four programmable ags provided for each FIFO:
Empty, partially empty, full, and partially full FIFO sta-
tus. The partially empty and partially full ags are pro-
grammable with the exibility to program the ags to
any value from the full or empty threshold. The pro-
grammed values can be set to a xed value through the
bitstream or a dynamic value can be controlled by input
pins of the EBR FIFO. When the FIFO is in asynchro-
nous mode, the FIFO ags use grey code counters to
ensure proper glitch-free operation.
Multiplier Modes
The ORCA Series 4 EBR supports two variations of
multiplier functions. Constant coefcient MULTIPLY
[KCM] mode will produce a 24-bit output of a xed 8-bit
constant multiply of a 16-bit number or a xed 16-bit
constant multiply of an 8-bit number. This KCM multi-
plies a constant times a 16- or 8-bit number and pro-
duces a product as a 24-bit result. The coefcient and
multiplication tables are stored in memory. The input
can be congured to be registered for pipelining. Both
write ports are available during MULTIPLY mode so
that the user logic can update and modify the coef-
cients for dynamic coefcient updates. The SCUBA
program in ORCA Foundry should be used to create
the KCM multipliers, including the input of initial coef-
cients.
An 8 x 8 MULTIPLY mode is congurable to either a
pipelined or combinatorial multiplier function of two 8-
bit numbers. Two 8-bit operands are multiplied to yield
a 16-bit product. The input can be registered in pipeline
mode.
CAM Mode
The CAM block is a binary content address memory
that provides fast address searches by receiving data
input and returning addresses that contain the data.
Implemented in each EBR are two 16-word x 8-bit CAM
function blocks.
The CAM has three modes, single match, multiple
match and clear, which are all achieved in one clock
cycle. In single match mode, a 8-bit data input is inter-
nally decoded and reports a match when data is
present in a particular RAM address. Its result is
reported by a corresponding single address bit. In mul-
tiple match the same occurs with the exception of multi-
ple address lines report the match. Clear mode is used
to clear the CAM contents by erasing all locations one
cycle per location. The EBR blocks in CAM mode may
be cascaded to produce larger CAMs.
相关PDF资料
PDF描述
OR4E042BA352-DB FPGA, 1296 CLBS, 380000 GATES, PBGA352
OR4E042BM416-DB FPGA, 1296 CLBS, 380000 GATES, PBGA416
OR4E042BM680-DB FPGA, 1296 CLBS, 380000 GATES, PBGA680
OR4E043BA352-DB FPGA, 1296 CLBS, 380000 GATES, PBGA352
OR4E043BM416-DB FPGA, 1296 CLBS, 380000 GATES, PBGA416
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OR4E04-2BM416I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256