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| 型号： | OR4E041BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 83/151页 |
| 文件大小： | 2680K |
| 代理商： | OR4E041BM680-DB |
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Lattice Semiconductor
37
Data Sheet
September, 2002
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
I/O Banks and Groups
Flexible I/O features allow the user to select the type of
I/O needed to meet different high-speed interface
requirements and these I/Os require different input ref-
erences or supply voltages. The perimeter of the device
is divided into eight banks of PIO buffers, as shown in
that supplies the correct input and output voltage for a
particular standard. The user must supply the appropri-
ate power supply to the VDDIO pin. Within a bank, sev-
eral I/O standards may be mixed as long as they use a
common VDDIO. The shaded section of the I/O banks in
Figure 23 (banks 2, 3, and 4) are removed for FPSCs,
to allow the embedded block to be placed on the side
of the FPGA array. Bank 1 and bank 5 are also
extended to the corners in FPSCs to incorporate more
FPGA I/Os.
Some interface standards require a specied threshold
voltage known as VREF. To accommodate various VREF
requirements, each bank is further divided into groups.
In these modes, where a particular VREF is required,
the device is automatically programmed to dedicate a
VREF pin for each group of PIOs within a bank. The
appropriate VREF voltage must be supplied by the user
and connected to the VREF pin for each group. The
VREF is dedicated exclusively to the group and cannot
be intermixed within the group with other signaling
requiring other VREF voltages. However, pins not
requiring VREF can be mixed in the same group. When
used to supply a reference voltage the VREF pad is no
longer available to the user for general use. The VREF
inputs should be well isolated to keep the reference
voltage at a consistent level.
Table17. Compatible Mixed I/O Standards
0205(F).
Figure 23. ORCA High-Speed I/O Banks
Differential I/O (LVDS and LVPECL)
Series 4 devices support differential input, output, and
input/output capabilities through pairs of PIOs. The two
standards supported are LVDS and LVPECL.
The LVDS differential pair I/O standard allows for high-
speed, low-voltage swing and low-power interfaces
dened by industry standards: ANSI/TIA/EIA-644 and
IEEE 1596.3 SSI-LVDS. The general purpose standard
is supplied without the need for an input reference sup-
ply and uses a low switching voltage which translates
to low ac power dissipation.
The ORCA LVDS I/O provides an integrated 100 ter-
mination resistor used to provide a differential voltage
across the inputs of the receiver. The on-chip integra-
tion provides termination of the LVDS receiver without
the need of discrete external board resistors. The user
has the programmable option to enable termination per
receiver pair for point-to-point applications or in multi-
point interfaces limit the use of termination to bussed
pairs. If the user chooses to terminate any differential
receiver, a single LVDS_R pin is dedicated to connect a
single 100 (± 1%) resistor to VSS which then enables
an internal resistor matching circuit to provide a bal-
ance 100 (± 10%) termination across all process,
voltage, and temperature. Experiments have also
shown that enabling this 100 matching resistor for
LVDS outputs also improves performance.
VDDIOBank
Voltage
CompatibleStandards
3.3VLVTTL,SSTL3-I,SSTL3-II,GTL+,
GTL,LVPECL,PECL
2.5VLVCMOS2,SSTL2-I,SSTL2-II,LVDS
1.8VLVCMOS18
1.5V
HSTLI,HSTLIII,HSTLIV
PLC ARRAY
(TC)
(TL)
(BC)
(BL)
(CL)
BANK 0
BANK 1
BANK 5
BANK 6
BANK
7
(TR)
(BR)
(CR)
BANK 2
BANK
3
BANK 4
相关PDF资料 |
PDF描述 |
|---|---|
| OR4E042BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E042BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| OR4E042BM680-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| OR4E043BA352-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA352 |
| OR4E043BM416-DB | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR4E04-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BA352C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BA352I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BM416C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR4E04-2BM416I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 466 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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