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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
168
Register 049H: T1 FRMR Interrupt Enable
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Reserved
COFAE
FERE
BEEE
SFEE
MFPE
INFRE
X
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF
bit of the Receive Options register is a logic 1, this register is held reset.
This register selects which of the MFP, COFA, FER, BEE, SFE or INFR events
generates an interrupt on the microprocessor INTB pin when their state changes
or their event condition is detected.
Reserved:
The Reserved bit is used for production test purposes only. The Reserved bit
must be programmed to logic 0 for normal operation.
COFAE:
The COFAE bit enables the generation of an interrupt when the frame find
circuitry determines that frame alignment has been achieved and that the
new alignment differs from the previous alignment. When COFAE is set to
logic 1, the declaration of a change of frame alignment is allowed to generate
an interrupt. When COFAE is set to logic 0, a change in the frame alignment
does not generate an interrupt on the INTB pin.
FERE:
The FERE bit enables the generation of an interrupt when a framing bit error
has been detected. When FERE is set to logic 1, the detection of a framing
bit error is allowed to generate an interrupt. When FERE is set to logic 0, any
error in the framing bits does not generate an interrupt on the INTB pin.