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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
374
packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be
enabled by setting the EN bit to logic 1. If no message is sent after the EN bit is
set to logic 1, continuous flags will be sent.
The TDPR can be used in a polled or interrupt driven mode for the transfer of
packet data. In the polled mode the processor controlling the TDPR must
periodically read the TDPR Interrupt Status register to determine when to write to
the TDPR Transmit Data register. In the interrupt driven mode, the processor
controlling the TDPR uses the INTB output to identify the interrupts which
determine when writes can or must be done to the TDPR Transmit Data register.
14.2.1 Automatic transmission mode using interrupts:
The TDPR automatically transmits a packet once it is completely written into the
TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level
exceeds the programmable Upper Transmit Threshold. The CRC bit can be set
to logic 1 so that the FCS is generated and inserted at the end of a packet. The
TDPR Lower Interrupt Threshold should be set to such a value that sufficient
warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits
are all set to logic 1 so an interrupt on INTB is generated upon detection of a
FIFO full state, a FIFO depth below the lower limit threshold, a FIFO overrun, or
a FIFO underrun. The following procedure should be followed to transmit HDLC
packets:
1. Wait for data to be transmitted. Once data is available to be transmitted, go
to step 2.
2. Write the data byte to the TDPR Transmit Data register.
3. If all bytes in the packet have been sent, set the EOM bit in the TDPR
Configuration register to logic 1. Go to step 1.
4. If there are more bytes in the packet to be sent, go to step 2.
While performing steps 1 to 4, the processor should monitor for interrupts
generated by the TDPR. When an interrupt is detected, the TDPR Interrupt
Routine should be executed.
The TDPR will force transmission of the packet information when the FIFO depth
exceeds the threshold programmed with the UTHR[6:0] bits in the TDPR Upper
Transmit Threshold register. Transmission will not stop until the last byte of all
complete packets is transmitted and the FIFO depth is at or below the threshold
limit. The user should watch the FULLI and LFILLI interrupts to prevent overruns
and underruns.