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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
272
Register 095H: E1 FRMR Maintenance/Alarm Status Interrupt Indication
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
RAII
RMAII
AISDI
Unused
REDI
AISI
FEBEI
CRCEI
X
X
X
X
X
X
X
X
R
R
R
R
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF
bit of the Receive Options register is a logic 1, this register is held reset.
A logic 1 in any bit position of this register indicates which maintenance or alarm
status generated an interrupt by changing state.
RAII, RMAII, AISDI, REDI, and AISI:
RAII, RMAII, AISDI, REDI, and AISI indicate when the corresponding FRMR
Maintenance/Alarm Status register bit has changed state from logic 0 to
logic 1 or vice-versa.
FEBEI:
The FEBEI bit becomes a logic one when a logic zero is received in the Si
bits of frames 13 or 15.
CRCEI:
The CRCEI bit becomes a logic one when a calculated CRC differs from the
received CRC remainder.
The bits in this register are set by a single error event.
The interrupt indications within this register work independently from the interrupt
enable bits, allowing the microprocessor to poll the register to determine the
state of the framer. The contents of this register are cleared to logic 0 after the
register is read; the interrupt is also cleared if it was generated by one of the
Maintenance/Alarm Status events.