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STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
362
CHI timing is configured by setting the BOFF_EN bit of the Transmit Backplane
Bit Offset register to a logic 1. In Figure 27, the FE register bit is set to logic 1 so
that BTFP is sampled on the rising edge of BTCLK. The DE register bit is set to
logic 0 so that BTPCM is sampled on the falling edge of BTCLK. CMS is set to
logic 1 so that the clock rate is equal to two times the data rate. BOFF[2:0] is set
to 'b001 so that the receive clock edge (CER) is equal to 11 (as determined by
the table in the Transmit Backplane Bit Offset register description of BOFF[2:0])
and BTPCM is sampled 11 clock edges after BTFP is sampled. TSOFF is set to
'b0000000 so that there is no time slot offset.
13.2 Receive Backplane Interface
By convention, the first bit transmitted in each timeslot shall be designated bit 0;
the last shall be bit 7.
Figure 28
- Receive Backplane at 1.544 Mbit/s (T1 Mode)
F
6
0
2
3
4
5
1
7
7
6
4
5
7
0
1
2
3
C
A
B
D
D
BRFP
1.544 MHz BRCLK
(CMS = 0)
BRPCM
BRSIG
Time Slot 23
Time Slot 0
F-bit or parity
6
4
5
0
1
2
3
C
A
B
D
C
A
B
D
7
Time Slot 1
X
X
X
A 1.544 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits
of the Receive Backplane Configuration register to 'b00 and the E1/T1B bit of the
Global Configuration register to a logic 0. In Figure 28, BRFP, BRPCM and
BRSIG are configured to be sampled on the falling edge of BRCLK by setting the
FE and DE bits of the Receive Backplane Configuration register to logic 0. The
TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero; therefore,
BRFP is aligned to the first bit of the frame. Once the RATE[1:0] bits are set, a
reset is required to change to a new RATE[1:0].