STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
359
Figure 21
- Transmit Backplane at 2.048 Mbit/s (E1 mode)
6
0
2
3
4
5
1
7
7
6
4
5
7
0
1
2
3
C
A
B
D
D
6
4
5
0
1
2
3
C
A
B
D
7
0
Time Slot 0
Time Slot 1
BTPCM
BTSIG
BTFP
2.048 MHz BTCLK
(CMS = 0)
4.096 MHz BTCLK
(CMS = 1)
Time Slot 31
X
X
X
X
A 2.048 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits
of the Transmit Backplane Configuration register to 'b01 and the E1/T1B bit of
the Global Configuration register to a logic 1. In Figure 21, BTFP, BTPCM and
BTSIG are configured to be sampled on the rising edge of BTCLK by setting the
FE and DE bits of the Transmit Backplane Configuration register to logic 1. Once
the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0].
The TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero;
therefore, BTFP is expected to be aligned to the first bit of the frame.
Figure 22
- Transmit Backplane at 4.096 Mbit/s (T1 mode)
TS 0
X
D
C
BTFP
4.096 MHz BTCLK
(CMS = 0)
BTPCM
BTSIG
X
TS 31
TS 1
X
X
TS 2
X
A
D
B
C
X
A
D
B
C
F
X
X
X
X
X
X
A 4.096 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits
of the Transmit Backplane Configuration register to 'b10 and the E1/T1B bit of
the Global Configuration register to a logic 0. In Figure 20, BTFP, BTPCM and
BTSIG are configured to be sampled on the rising edge of BTCLK by setting the
FE and DE bits of the Transmit Backplane Configuration register to logic 1.
TSOFF[6:0] is set to 'b0000000 so that the first of the two interleaved bytes is
sampled. Once the RATE[1:0] bits are set, a reset is required to change to a new
RATE[1:0].
In Figure 20, the MAP bit of the Transmit Backplane Frame Pulse Configuration
register is a logic 0. Therefore, every fourth time slot is unused, starting with
timeslot 0. The framing bit is sampled during bit 0 of time slot 0, so that only bits
1 to 7 of time slot 0 are ignored. If MAP is logic 1, the 24 T1 channels would be
aligned to the first 24 timeslots with the F-bit located in the last bit of the 32
nd
timeslot.