STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
316
will expect appropriately placed zero suppression bits when QRSS is a
logic 1.
PS:
The PS bit selects the pattern type. When PS is a logic 1, a repetitive pattern
is generated. When PS is a logic 0, a pseudo-random pattern is
generated/detected. The PS bit must be programmed to the desired setting
before programming any other PRGD registers, otherwise the transmitted
pattern may be corrupted. Any time the setting of the PS bit is changed, the
rest of the PRGD registers should be reprogrammed.
TINV:
The TINV bit controls the logical inversion of the generated pattern. When
TINV is a logic 1, the data generated is inverted.
RINV:
The RINV bit controls the logical inversion of the received stream. When
RINV is a logic 1, the received data is inverted before being processed by the
pattern detector.
AUTOSYNC:
The AUTOSYNC bit enables the automatic resynchronization of the pattern
detector. The automatic resynchronization is activated when 10 or more bit
errors are detected in a fixed 48-bit window. When AUTOSYNC is a logic 1,
the auto resync feature is enabled. When AUTOSYNC is a logic 0, the auto
sync feature is disabled, and pattern resynchronization is accomplished using
the MANSYNC bit.
MANSYNC:
The MANSYNC bit is used to initiate a manual resynchronization of the
pattern detector. A low to high transition on MANSYNC initiates the
resynchronization.