STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
265
Register 090H: E1 FRMR Frame Alignment Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
CRCEN
CASDIS
C2NCIWCK
Unused
Reserved
REFR
REFCRCEN
REFRDIS
1
0
0
X
0
0
1
0
R/W
R/W
R/W
R/W
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF
bit of the Receive Options register is a logic 1, this register is held reset.
This register selects the various framing formats and framing algorithms
supported by the FRMR block.
CRCEN:
The CRCEN bit enables the FRMR to frame to the CRC multiframe. When
the CRCEN bit is logic 1, the FRMR searches for CRC multiframe alignment
and monitors for errors in the alignment. A logic 0 in the CRCEN bit position
disables searching for multiframe and suppresses the OOCMF, CRCE,
CMFER, FEBE, CFEBE, RAICCRC, C2NCIW and ICMFPI FRMR
status/interrupt bits, forcing them to logic 0.
CASDIS:
The CASDIS bit enables the FRMR to frame to the Channel Associated
Signaling multiframe when set to a logic 0. When CAS is enabled, the FRMR
searches for signaling multiframe alignment and monitors for errors in the
alignment. A logic 1 in the CASDIS bit position disables searching for
multiframe and suppresses the OOSMF and the SMFER FRMR outputs,
forcing them to logic 0.
C2NCIWCK:
The C2NCIWCK bit enables the continuous checking for CRC multiframe in
the CRC to non-CRC interworking mode of the E1 FRMR. If this bit is a
logic 0, the E1-FRMR will cease searching for CRC multiframe alignment in
CRC to non-CRC interworking mode. If this bit is a logic 1, the E1-FRMR will