STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
378
When an abort character is received, another dummy byte and link down status
is written into the FIFO. This is done to provide alignment of link down status
with the data read from the FIFO. It is up to the controlling processor to check
the COLS Status Register bit for a change in the link status. If the COLS Status
Register bit is set to logic 1, the FIFO must be emptied to determine the current
link status. The first flag and abort status encoded in the PBS bits is used to set
and clear a Link Active software flag.
When the last byte of a properly terminated packet is received, an interrupt is
generated. When the Status Register is read the PKIN bit will be logic 1. This
can be a signal to the external processor to empty the bytes remaining in the
FIFO or to just increment a number-of-packets-received count and wait for the
FIFO to fill to a programmable level. Once the Status Register is read, the PKIN
bit is cleared to logic 0 . If the Status Register is read immediately after the last
packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the CRC and
non-integer byte status can be checked by reading the PBS[1:0] bits.
When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must
be emptied to remove this source of interrupt.
The RDLC can be used in a polled or interrupt driven, or DMA-controlled mode
for the transfer of frame data. In the polled mode, the INTB output is not used,
and the processor controlling the RDLC must periodically read the Status
Register of the RDLC to determine when to read the Data Register. In the
interrupt driven mode, the processor controlling the RDLC uses the INTB output
to determine when to read the Data Register.
In the case of interrupt driven data transfer from the RDLC to the processor, the
INTB output of the RDLC is connected to the interrupt input of the processor.
Once the processor has determined the RDLC is the source of the interrupt, the
interrupt service routine should process the data in the following order:
1. RDLC Status Register Read. If INTR=1 then proceed to step 2 else find the
interrupt source elsewhere.
2. If OVR = 1, discard last frame and go to step 1. Overrun causes a reset of
FIFO pointers. Any packets that may have been in the FIFO are lost.
3. If COLS = 1, set the EMPTY FIFO software flag.
4. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be
emptied as soon as a complete packet is received, set the EMPTY FIFO
software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will
be delayed until the FIFO fill level is exceeded.
5. Data Register Read.