STANDARD PRODUCT
PM4351 COMET
DATA SHEET
PMC-1970624
ISSUE 10
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
266
continue searching for CRC multiframe alignment, even if CRC to non-CRC
interworking has been declared.
Reserved:
The Reserved bit must be programmed to logic 0 for normal operation.
REFR:
A transition from logic 0 to logic 1 in the REFR bit position forces the re-
synchronization to a new frame alignment. The bit must be cleared to logic 0,
then set to logic 1 again to generate subsequent re-synchronizations.
REFCRCEN:
The REFCRCEN bit enables excessive CRC errors (
≥
915 errors in one
second) to force a re-synchronization to a new frame alignment. Setting the
REFCRCEN bit position to logic 1 enables reframe due to excessive CRC
errors; setting the REFCRCEN bit to logic 0 disables CRC errors from
causing a reframe.
REFRDIS:
The REFRDIS bit disables reframing under any error condition once frame
alignment has been found; reframing can be initiated by software via the
REFR bit. A logic 1 in the REFRDIS bit position causes the FRMR to remain
"locked in frame" once initial frame alignment has been found. A logic 0
allows reframing to occur based on the various error criteria (FER, excessive
CRC errors, etc.). Note that while the FRMR remains locked in frame due to
REFRDIS=1, a received AIS will not be detected since the FRMR must be
out-of-frame to detect AIS.